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base repository: m-labs/nmigen
base: 56bb42aff279
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head repository: m-labs/nmigen
compare: f8428ff5051c
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  • 1 commit
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  • 1 contributor

Commits on Nov 27, 2019

  1. back.rtlil: infer bit width for instance parameters. 

    Otherwise, Yosys assumes it is always 32, which is often
inappropriate.
    whitequark committed Nov 27, 2019
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