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base repository: m-labs/nmigen
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base: 56bb42aff279
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head repository: m-labs/nmigen
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compare: f8428ff5051c
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Nov 27, 2019

  1. back.rtlil: infer bit width for instance parameters.

    Otherwise, Yosys assumes it is always 32, which is often
    inappropriate.
    whitequark committed Nov 27, 2019
    Copy the full SHA
    f8428ff View commit details
Showing with 2 additions and 2 deletions.
  1. +2 −2 nmigen/back/rtlil.py
4 changes: 2 additions & 2 deletions nmigen/back/rtlil.py
Original file line number Diff line number Diff line change
@@ -128,8 +128,8 @@ def cell(self, kind, name=None, params={}, ports={}, attrs={}, src=""):
self._append(" parameter \\{} \"{}\"\n",
param, value.translate(self._escape_map))
elif isinstance(value, int):
self._append(" parameter \\{} {:d}\n",
param, value)
self._append(" parameter \\{} {}'{:b}\n",
param, bits_for(value), value)
elif isinstance(value, float):
self._append(" parameter real \\{} \"{!r}\"\n",
param, value)