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base repository: m-labs/nmigen
base: 29f7a3c6182a
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head repository: m-labs/nmigen
compare: b70c836b96c7
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  • 11 commits
  • 8 files changed
  • 2 contributors

Commits on Sep 30, 2019

  1. rpc: add support for Yosys RPC protocol.

    whitequark committed Sep 30, 2019
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  2. rpc: add public Records as module ports.

    Jean-François Nguyen authored and whitequark committed Sep 30, 2019
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Commits on Oct 2, 2019

  1. back.rtlil: it is not necessary to match binop operand width.

    whitequark committed Oct 2, 2019
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  2. back.rtlil: sign of rhs and lhs of ${sshr,sshl,pow} don't need to match.

    whitequark committed Oct 2, 2019
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  3. back.rtlil: don't cache wires for legalized switch tests. 

    This causes miscompilation of code such as:

  r = Array([self.a, self.b])
  m = Module()
  with m.If(r[self.s]):
      m.d.comb += self.o.eq(1)
  return m
    whitequark committed Oct 2, 2019
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  4. hdl.ast: don't crash on Mux(<bool>, ...). 

    Fixes #240.
    whitequark committed Oct 2, 2019
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Commits on Oct 3, 2019

  1. build.dsl: accept Pins(invert=True). 

    The PinsN() form is still preferred, but Pins(invert=) form is useful
for code generic over pin polarity.
    whitequark committed Oct 3, 2019
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Commits on Oct 4, 2019

  1. hdl.ast: prohibit signed divisors. 

    See #238.
    whitequark committed Oct 4, 2019
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  2. back.rtlil: avoid unsoundness for division by zero. 

    Fixes #238.
    whitequark committed Oct 4, 2019
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Commits on Oct 6, 2019

  1. back.rtlil: don't crash legalizing values with no branches. 

    Fixes #239.
    whitequark committed Oct 6, 2019
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Commits on Oct 9, 2019

  1. vendor.intel: add Quartus support. (WIP)

    whitequark committed Oct 9, 2019
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