Commits on Oct 9, 2019

1. build.plat,vendor: always synchronize reset in default sync domain. …

   This change achieves two related goals.
   
   First, default_rst is no longer assumed to be synchronous to
   default_clk, which is  the safer option, since it can be connected to
   e.g. buttons on some evaluation boards.
   
   Second, since the power-on / configuration reset is inherently
   asynchronous to any user clock, the default create_missing_domain()
   behavior is to use a reset synchronizer with `0` as input. Since,
   like all reset synchronizers, it uses Signal(reset=1) for its
   synchronization stages, after power-on reset it keeps its subordinate
   clock domain in reset, and releases it after fabric flops start
   toggling.
   
   The latter change is helpful to architectures that lack an end-of-
   configuration signal, i.e. most of them. ECP5 was already using
   a similar scheme (and is not changed here). Xilinx devices with EOS
   use EOS to drive a BUFGMUX, which is more efficient than using
   a global reset when the design does not need one; Xilinx devices
   without EOS use the new scheme. iCE40 requires a post-configuration
   timer because of BRAM silicon bug, and was changed to add a reset
   synchronizer if user clock is provided.

   whitequark committed Oct 9, 2019
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