Now that placement of non-IO clusters and capacity clusters is supported (after #1230 is merged), a first pass clock placer could be created in prjxray_create_place_constraints.py to avoid needing to manually add LOC constraints on clock items.

Rough algorithm:

• Identify clock relevant items (CCIO IBUFs, PLL's/MMCM's, BUFG's, etc)
• Attempt to build clock network that follows rules from https://www.xilinx.com/support/documentation/user_guides/ug472_7Series_Clocking.pdf
  • Generate an error if this is not possible
• Emit VPR placement constraints

As a first pass the important rules to implement are:

• If a PLL/MMCM any of the clock sources are CCIO inputs, then the PLL/MMCM should be placed in the same CMT
• The source of BUFG must match whether it is placed in the top or bottom CLK_BUFG tile