On Mon, 25 Nov 2019 at 01:27, Maciej Kurc ***@***.***> wrote: Since BLIF file cannot handle inout ports, these are represented as a single net connected to both input and output port with the same name. This creates an issue when something drives that net as there are multiple drivers there. Currently to solve this we use the following flow: - Synthesize the design using Yosys but write it to JSON instead of BLIF. - Process the JSON using a python script that splits inout ports to separate input and output ports. - Load the JSON to Yosys again and write the final BLIF (this is essentially a format conversion). The "as it should be done" solution would be to have a plugin for Yosys that does the inout port split. That would allow to get rid of the need for writing JSONs and processing them. — You are receiving this because you are subscribed to this thread. Reply to this email directly, view it on GitHub <#1172>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AAAFFXHUM6ECBMUS4ECL4FLQVOLATANCNFSM4JRF5O5A> .