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PLL and BUFG need to be placed in the same clock row region #1182

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acomodi opened this issue Nov 26, 2019 · 3 comments
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PLL and BUFG need to be placed in the same clock row region #1182

acomodi opened this issue Nov 26, 2019 · 3 comments

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@acomodi
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acomodi commented Nov 26, 2019

There are several situations for which the clock is being routed from the PLL output to the BUFG tile that are placed in incompatible locations.

Incompatible location example:

  • PLL placed in TOP half (e.g. X1Y1)
  • BUFG placed in BOTTOM half (e.g. X0Y0).

In such a situation, nor the BUFG output can be driven to the PLL clk input neither PLL output to BUFG input.

This situation causes fasm2bels to fail, as well a non-working output bitstream produced with the symbiflow toolchain.
@acomodi acomodi mentioned this issue Nov 26, 2019
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@acomodi
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acomodi commented Nov 26, 2019 •
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@litghost @tmichalak FYI

This was referenced Nov 27, 2019
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@acomodi acomodi mentioned this issue Dec 10, 2019
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@litghost
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I've proposed #1231 as a solution to this issue.

@acomodi
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acomodi commented Jan 8, 2020

Closing. Fixed with #1237

@acomodi acomodi closed this as completed Jan 8, 2020
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@litghost @acomodi