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AsyncFIFO/AsyncFIFOBuffered do not infer BRAMs on iCE40 #172

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whitequark opened this issue Aug 18, 2019 · 3 comments
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AsyncFIFO/AsyncFIFOBuffered do not infer BRAMs on iCE40 #172

whitequark opened this issue Aug 18, 2019 · 3 comments
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bug toolchain:yosys upstream
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0.1

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@whitequark
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AsyncFIFO specifies a transparent read port and that doesn't work on iCE40 across clock domains because it can only insert soft transparency logic. (How did this work on oMigen in the first place?)

This needs to be investigated closely.
@whitequark
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whitequark commented Aug 18, 2019 •
edited

How did this work on oMigen in the first place?

Answer: it does not. oMigen's AsyncFIFO[Buffered] with master Yosys does not synthesize into BRAM on iCE40.

@whitequark
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I think this might be because the read port is transparent (as is the default for Memory.read_port(); we should probably make that explicit). But it doesn't make a lot of sense to have a transparent read port on a memory where both ports are in different domains.

How did this work before? Did oMigen emit the wrong kind of read port, and Xilinx quietly ignore it?

@whitequark
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This is apparently a Yosys bug, YosysHQ/yosys#1390.

@whitequark whitequark added this to the 0.1 milestone Sep 20, 2019
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