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With the core language feature-complete, the build system nearing maturity, and the library gaining many important primitives, it is time to indicate that nMigen can be used in practical designs by people not closely involved in its development. (I've heard that there is a lot of interest in that.) In this issue I outline what I see as prerequisites to milestone 0.1.
Creation of clock domains (or lack thereof) is an important UI issue. In particular, it seems like everyone gets domain propagation wrong at first, so if people don't have to explicitly create ClockDomain objects either to convert an isolated module to Verilog or to use the platform with just a single clock domain, it would eliminate a lot of beginner papercuts. That's Fragment.prepare should allow caller to handle nonexistent clock domains #57.
Although not an issue that affects semantics, generated Verilog being unreadable is a significant annoyance to people who has an easier time reading Verilog than RTLIL, i.e. basically everyone. That's Generated Verilog should be more readable #98. Unfortunately it missed the merge window for Yosys 0.9, so we'll have to highlight it in README, emit a warning (ugh), or something like that.
Regardless of the standard library items that should be added to reach 0.1 (which is subject to some discussion), the standard library items that are already in master should not have their most basic interface change after 0.1. That means applying the new convention from Bikeshed: conventions for CDC primitives #97.
@Wren6991 did some very good work porting CDC primitives from oMigen, and it would be a shame if it missed 0.1, especially as there are no outstanding issues I can see, and it would give us a big improvement towards oMigen compatibility.
Now there are some issues that I think shouldn't block 0.1, but I'm open to feedback:
Synchronous transparent read ports (Support transparent ports with RE #16); lack of such ports was a problem in Minerva, so it does come up in real designs. Unfortunately this both misses the Yosys 0.9 merge window, and is quite nontrivial to actually implement. I think it's more of a 0.2 issue.
3\. Although not an issue that affects semantics, generated Verilog being unreadable is a significant annoyance to people who has an easier time reading Verilog than RTLIL, i.e. basically everyone.
There are also people who will judge the tool based on the quality of the generated Verilog.
Most of the issues here have been resolved. Since I will likely rewrite the simulator for 0.2, simulator bugs (#28, #34, #47) are postponed until that point. The remaining issues in the 0.1 milestone should be the last ones that I expect to add.
With the core language feature-complete, the build system nearing maturity, and the library gaining many important primitives, it is time to indicate that nMigen can be used in practical designs by people not closely involved in its development. (I've heard that there is a lot of interest in that.) In this issue I outline what I see as prerequisites to milestone 0.1.
Creating signals named like verilog keywords produces invalid verilog #53. We should check for Yosys version inback.verilog
as well, which isShould nMigen check Yosys version? #55.ClockDomain
objects either to convert an isolated module to Verilog or to use the platform with just a single clock domain, it would eliminate a lot of beginner papercuts. That'sFragment.prepare should allow caller to handle nonexistent clock domains #57.Bikeshed: conventions for CDC primitives #97.Now there are some issues that I think shouldn't block 0.1, but I'm open to feedback:
Every other outstanding issue is more of a nice-to-have and shouldn't count here.
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