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base repository: m-labs/nmigen
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compare: f207f3f62098
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  • 1 commit
  • 3 files changed
  • 1 contributor

Commits on Nov 18, 2019

  1. vendor.xilinx_*: Set IOB attribute on cels instead of nets.

    Jean-François Nguyen authored and whitequark committed Nov 18, 2019
    Copy the full SHA
    f207f3f View commit details
Showing with 6 additions and 18 deletions.
  1. +2 −7 nmigen/vendor/xilinx_7series.py
  2. +2 −4 nmigen/vendor/xilinx_spartan_3_6.py
  3. +2 −7 nmigen/vendor/xilinx_ultrascale.py
9 changes: 2 additions & 7 deletions nmigen/vendor/xilinx_7series.py
Original file line number Diff line number Diff line change
@@ -175,19 +175,14 @@ def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
def get_dff(clk, d, q):
# SDR I/O is performed by packing a flip-flop into the pad IOB.
for bit in range(len(q)):
_q = Signal()
_q.attrs["IOB"] = "TRUE"
# Vivado 2019.1 seems to make this flip-flop ineligible for IOB packing unless
# we prevent it from being optimized.
_q.attrs["DONT_TOUCH"] = "TRUE"
m.submodules += Instance("FDCE",
a_IOB="TRUE",
i_C=clk,
i_CE=Const(1),
i_CLR=Const(0),
i_D=d[bit],
o_Q=_q
o_Q=q[bit]
)
m.d.comb += q[bit].eq(_q)

def get_iddr(clk, d, q1, q2):
for bit in range(len(q1)):
6 changes: 2 additions & 4 deletions nmigen/vendor/xilinx_spartan_3_6.py
Original file line number Diff line number Diff line change
@@ -212,16 +212,14 @@ def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
def get_dff(clk, d, q):
# SDR I/O is performed by packing a flip-flop into the pad IOB.
for bit in range(len(q)):
_q = Signal()
_q.attrs["IOB"] = "TRUE"
m.submodules += Instance("FDCE",
a_IOB="TRUE",
i_C=clk,
i_CE=Const(1),
i_CLR=Const(0),
i_D=d[bit],
o_Q=_q,
o_Q=q[bit]
)
m.d.comb += q[bit].eq(_q)

def get_iddr(clk, d, q0, q1):
for bit in range(len(q0)):
9 changes: 2 additions & 7 deletions nmigen/vendor/xilinx_ultrascale.py
Original file line number Diff line number Diff line change
@@ -175,19 +175,14 @@ def _get_xdr_buffer(self, m, pin, *, i_invert=False, o_invert=False):
def get_dff(clk, d, q):
# SDR I/O is performed by packing a flip-flop into the pad IOB.
for bit in range(len(q)):
_q = Signal()
_q.attrs["IOB"] = "TRUE"
# Vivado 2019.1 seems to make this flip-flop ineligible for IOB packing unless
# we prevent it from being optimized.
_q.attrs["DONT_TOUCH"] = "TRUE"
m.submodules += Instance("FDCE",
a_IOB="TRUE",
i_C=clk,
i_CE=Const(1),
i_CLR=Const(0),
i_D=d[bit],
o_Q=_q
o_Q=q[bit]
)
m.d.comb += q[bit].eq(_q)

def get_iddr(clk, d, q1, q2):
for bit in range(len(q1)):