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Constant sign-extends incorrectly. #271
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Does it work correctly if you simulate the design? |
Yes. pysim subtracts one. |
Since both the Verilog and simulation behavior is correct, this isn't an nMigen bug. |
The generated Verilog is incorrect since a 1 bit signed value can only have the values -1 and 0. nmigen should zero-extend unsigned values when converting them to See also: C++ example on Compiler Explorer. |
Ah, hm. You're right, I missed that it was 1-bit. That's troublesome. |
I confirm that the fix works for my code. Thank you. |
This program shows that subtracting 1 from a signed signal actually adds one.
The generated Verilog shows this statement. I think Yosys sign-extends
$signed(1'h1)
to24'b111111111111111111111111
before subtracting.Versions:
nMigen v0.1
Yosys 0.9+932 (git sha1 ab0fb19c, clang 11.0.0 -fPIC -Os)
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