Does it work correctly if you simulate the design?

Yes. pysim subtracts one.

Since both the Verilog and simulation behavior is correct, this isn't an nMigen bug.

The generated Verilog is incorrect since a 1 bit signed value can only have the values -1 and 0. nmigen should zero-extend unsigned values when converting them to
a wider signed type. The integer type conversion is needed since Verilog doesn't have (as far as I know) operations that have one signed and one unsigned operand.

See also: C++ example on Compiler Explorer.

Ah, hm. You're right, I missed that it was 1-bit. That's troublesome.

I confirm that the fix works for my code. Thank you.