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Enumerated signals? #198
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You can use: @classmethod
def signal(cls):
return Signal.range(0, MCycle._next.value - 1, src_loc_at=1) to tell nMigen which stack frame to get the variable name from. You can also remove @classmethod
def signal(cls):
return Signal.range(min(v.value for k,v in Enum.__members__.items()),
max(v.value for k,v in Enum.__members__.items()) + 1,
src_loc_at=1) Otherwise, this code is idiomatic. |
Incidentally, instead of clk = Signal()
rst = Signal()
pos = ClockDomain()
pos.clk = clk
pos.rst = rst
# ...
main(m, ports=[clk, rst] + cycler.ports(), platform="formal") you should probably use
|
Ah, |
Works, thanks! |
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What's the nMigen way of creating an enumerated signal, that is, a signal with a binary encoding whose values are named, possibly having some tie to Python Enums?
This seems to work:
However, the generated Verilog seems to use the name
\$signal
formcycle
.Replacing
self.mcycle = MCycle.signal()
withself.mcycle = Signal.range(0, MCycle._next.value - 1)
causes the generated Verilog to usemcycle
as the name instead.So:
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