How to simulate with two clock domains? #236
Comments
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This is currently broken for reasons that are not entirely clear. See #28. I plan to rewrite the simulator entirely, since it has a number of serious flaws that require changing core decisions, but this will take some time. A possible workaround is to use Another possible workaround is to use https://github.com/andresdemski/nmigen-cocotb. (I have not personally used it.) I will also take a good look at cocotb's user interface (see #228), so if later you want to get rid of cocotb in favor of Python-only simulation, it is likely that the migration would not be very painful. |
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@RobertBaruch Have you been able to use one of these workarounds? |
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I haven't looked at it yet. I can try nmigen-cocotb. |
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Tried nmigen-cocotb, but apparently nothing is output. I get a sim_build directory with a vvp file. I did run vvp on that vvp file and got an output.vcd, which contained no signal changes. Maybe there's some documentation out of date -- the test runner doesn't seem to run the function annotated with from nmigen import *
# from nmigen.cli import main
from nmigen.asserts import *
# from nmigen.back import pysim
# from nmigen.hdl.ast import Tick
# module edgelord outputs the state of the clock without using
# the clock in combinatorial logic. This is a good thing in
# FPGAs, where the clock is a special signal that might get
# badly routed if it has to go through anything other than the
# clock inputs of flipflops.
#
# The reset signal MUST be held high for both edges,
# otherwise the clk_state will be inverted.
class Edgelord(Elaboratable):
def __init__(self):
self.clk_state = Signal()
self.unfunf = Signal()
def elaborate(self, platform):
pos = Signal()
neg = Signal()
rst = ResetSignal("pos")
m = Module()
# Verilog equivalent:
#
# assign clk_state = reset || !(pos ^ neg);
m.d.comb += self.clk_state.eq(rst | ~(pos ^ neg))
# Verilog equivalent:
#
# always @(posedge clk) begin
# if (reset) pos <= 0;
# else pos <= !(pos ^ clk_state);
# end
#
# always @(negedge clk) begin
# if (reset) neg <= 0;
# else neg <= neg ^ clk_state;
# end
m.d.neg += self.unfunf.eq(~self.unfunf)
with m.If(rst):
m.d.pos += pos.eq(0)
m.d.neg += neg.eq(0)
with m.Else():
m.d.pos += pos.eq(~(pos ^ self.clk_state))
m.d.neg += neg.eq(neg ^ self.clk_state)
return m
from nmigen_cocotb import run, get_current_module
import cocotb
from cocotb.triggers import Timer
def tick(dut):
print("tick\n")
dut.clk <= 0
yield Timer(10, 'ns')
dut.clk <= 1
yield Timer(10, 'ns')
@cocotb.test()
def reset_test(dut):
print("start reset_test\n")
dut._log.info("Running test!")
dut.rst <= 1
tick(dut)
tick(dut)
dut.rst <= 0
tick(dut)
tick(dut)
tick(dut)
dut._log.info("Test complete!")
def test_module():
clk = Signal()
rst = Signal()
pos = ClockDomain()
pos.clk = clk
pos.rst = rst
neg = ClockDomain(clk_edge="neg")
neg.clk = clk
neg.rst = rst
edgelord = Edgelord()
m = Module()
m.domains.pos = pos
m.domains.neg = neg
m.submodules.edgelord = edgelord
print("Start run\n")
run(m, get_current_module(), ports=[clk, rst, edgelord.clk_state], vcd_file='output.vcd')
if __name__ == "__main__":
print("Running\n")
test_module() |
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Hmm, the coctb-nmigen example doesn't even output anything, so there must be some step missing. |
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Yeah, no. |
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What about my other suggestion? |
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Working on that now! |
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Sorry, I'm going to need more explicit instructions on what to do with |
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Something like: |
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Yes, that seems to have worked, thanks! |
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Hi, get_current_module function is not working currently in nmigen-cocotb. Try to use it with harcoded module. |
What's the right pattern to use? Here is an example of what I've tried:
This resulted in:
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