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Build breaks with the latest abc: error: cast from pointer to smaller type 'ABC_PTRINT_T' (aka 'int') loses information #305

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yurivict opened this issue Oct 26, 2019 · 2 comments
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Build breaks with the latest abc: error: cast from pointer to smaller type 'ABC_PTRINT_T' (aka 'int') loses information #305

yurivict opened this issue Oct 26, 2019 · 2 comments

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@yurivict
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yurivict commented Oct 26, 2019 •
edited 

In file included from /usr/local/include/abc/misc/vec/vec.h:29:
/usr/local/include/abc/misc/util/abc_global.h:314:77: error: cast from pointer to smaller type 'ABC_PTRINT_T' (aka 'int') loses information
static inline int      Abc_Ptr2Int( void * p )                { return (int)(ABC_PTRINT_T)p;      }
                                                                            ^~~~~~~~~~~~~~~
/usr/local/include/abc/misc/util/abc_global.h:316:78: error: cast from pointer to smaller type 'ABC_PTRUINT_T' (aka 'unsigned int') loses information
static inline word     Abc_Ptr2Wrd( void * p )                { return (word)(ABC_PTRUINT_T)p;    }
                                                                             ^~~~~~~~~~~~~~~~
/usr/local/include/abc/misc/util/abc_global.h:333:43: warning: '__APPLE__' is not defined, evaluates to 0 [-Wundef]
#if (defined(LIN) || defined(LIN64)) && !(__APPLE__ & __MACH__) && !defined(__MINGW32__)
                                          ^
/usr/local/include/abc/misc/util/abc_global.h:333:55: warning: '__MACH__' is not defined, evaluates to 0 [-Wundef]
#if (defined(LIN) || defined(LIN64)) && !(__APPLE__ & __MACH__) && !defined(__MINGW32__)
                                                      ^

clang-8 on FreeBSD.

Version 8.0.0_rc1
abc f9309ce
@litghost
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litghost commented Oct 28, 2019 •
edited by unfurl-links bot

This issue and the other build failures appear to be present in upstream VTR (https://github.com/verilog-to-routing/vtr-verilog-to-routing), so this issue should be tracked and fixed there. Symbiflow/vtr-verilog-to-routing is a downstream fork, and changes like this should be made upstream, and Symbiflow will integrate them.

GitHub
Verilog to Routing -- Open Source CAD Flow for FPGA Research - verilog-to-routing/vtr-verilog-to-routing

@yurivict
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verilog-to-routing#1017

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@yurivict @litghost