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Multiclock simulation broken #28

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whitequark opened this issue Jan 26, 2019 · 6 comments
Closed

Multiclock simulation broken #28

whitequark opened this issue Jan 26, 2019 · 6 comments
Labels
backend:simulator bug
Milestone
0.2

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@whitequark
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Repro:

from nmigen import *
from nmigen.back.pysim import *


m = Module()
m.domains += ClockDomain("input")
m.domains += ClockDomain("output")

with Simulator(m, vcd_file=open("test.vcd", "w")) as sim:
    sim.add_clock(3e-6, domain="input")
    sim.add_clock(5e-6, domain="output")
    sim.run_until(1, run_passive=True)
@whitequark whitequark added the bug label Jan 26, 2019
@Wren6991 Wren6991 mentioned this issue Apr 10, 2019
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@whitequark whitequark added this to the 0.2 milestone Sep 20, 2019
@RobertBaruch
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Apparently when the two clocks need to change at the same time (here, at 7.5us), at timestamp 7.5, the scheduled events are at 7.5 and 10, with a delta of 1e-10. Since 7.5-min(7.5, 10)=0 <= 1e-10, a DeadlineError is raised.

You probably already know this :)

$ python3 simclk.py
step
  curr_dirty any
    wait_deadline {}, ts 0.0, delta 0.0
step
  processes > suspended
step
  processes > suspended
step
  run passive
step
  curr_dirty any
    wait_deadline {<generator object Simulator.add_clock.<locals>.clk_process at 0x7f447bd295c8>: 2.5, <generator object Simulator.add_clock.<locals>.clk_process at 0x7f447bd29620>: 3.0}, ts 1.5, delta 1e-10
     wait_deadline.values dict_values([2.5, 3.0])
step
  run passive
step
  curr_dirty any
    wait_deadline {<generator object Simulator.add_clock.<locals>.clk_process at 0x7f447bd29620>: 3.0, <generator object Simulator.add_clock.<locals>.clk_process at 0x7f447bd295c8>: 5.0}, ts 2.5, delta 1e-10
     wait_deadline.values dict_values([3.0, 5.0])
step
  run passive
step
  curr_dirty any
    wait_deadline {<generator object Simulator.add_clock.<locals>.clk_process at 0x7f447bd295c8>: 5.0, <generator object Simulator.add_clock.<locals>.clk_process at 0x7f447bd29620>: 4.5}, ts 3.0, delta 0.0
     wait_deadline.values dict_values([5.0, 4.5])
step
  run passive
step
  curr_dirty any
    wait_deadline {<generator object Simulator.add_clock.<locals>.clk_process at 0x7f447bd295c8>: 5.0, <generator object Simulator.add_clock.<locals>.clk_process at 0x7f447bd29620>: 6.0}, ts 4.5, delta 1e-10
     wait_deadline.values dict_values([5.0, 6.0])
step
  run passive
step
  curr_dirty any
    wait_deadline {<generator object Simulator.add_clock.<locals>.clk_process at 0x7f447bd29620>: 6.0, <generator object Simulator.add_clock.<locals>.clk_process at 0x7f447bd295c8>: 7.5}, ts 5.0, delta 0.0
     wait_deadline.values dict_values([6.0, 7.5])
step
  run passive
step
  curr_dirty any
    wait_deadline {<generator object Simulator.add_clock.<locals>.clk_process at 0x7f447bd295c8>: 7.5, <generator object Simulator.add_clock.<locals>.clk_process at 0x7f447bd29620>: 7.5}, ts 6.0, delta 0.0
     wait_deadline.values dict_values([7.5, 7.5])
step
  run passive
step
  curr_dirty any
    wait_deadline {<generator object Simulator.add_clock.<locals>.clk_process at 0x7f447bd29620>: 7.5, <generator object Simulator.add_clock.<locals>.clk_process at 0x7f447bd295c8>: 10.0}, ts 7.5, delta 1e-10
     wait_deadline.values dict_values([7.5, 10.0])
Traceback (most recent call last):
  File "simclk.py", line 11, in <module>
    sim.run_until(100, run_passive=True)
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/back/pysim.py", line 854, in run_until
    if not self.step(run_passive):
  File "/home/robertbaruch/.local/lib/python3.6/site-packages/nmigen/back/pysim.py", line 810, in step
    raise DeadlineError("Delta cycles exceeded process deadline; combinatorial loop?")
nmigen.back.pysim.DeadlineError: Delta cycles exceeded process deadline; combinatorial loop?

@whitequark
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You probably already know this :)

I actually did not have a chance to look into this. Do you happen to have a patch?

@RobertBaruch
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RobertBaruch commented Oct 13, 2019 •
edited

No, I just noted the immediate cause of the error, not the root cause, since I have no idea how the simulator works. Still looking into that.

@RobertBaruch
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I just removed the check. I know nothing about how the simulator works, but the comment mentions logic loops. These clocks seem to be implemented as two processes with no inputs, so maybe the check should be done minus any processes which are clocks?

@whitequark
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Mm, not sure, sorry. I don't remember much about the simulator, and I've focused most of my mental effort on a future complete redesign.

@RobertBaruch
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In any case, even with that change, it doesn't seem like anything associated with the negative edge of the clock changes in the simulator (see #236), so now there are two problems :)

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