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Model for DFF with enable input is generated with combinational port relation #25

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mglb opened this issue Dec 17, 2019 · 0 comments

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mglb commented Dec 17, 2019

Input file (ff.sim.v):

(* whitebox *)
module FF(clk, D, E, Q);
	input wire clk;
	(* SETUP="clk 10e-12" *)
	input wire D;
	(* SETUP="clk 10e-12" *)
	input wire E;
	(* CLK_TO_Q = "clk 10e-12" *)
	output reg Q;
	always @(posedge clk) begin
		if (E)
			Q <= D;
	end
endmodule

Generated model (ff.model.xml):

<models xmlns:xi="http://www.w3.org/2001/XInclude">
  <model name="FF">
    <input_ports>
      <port name="D" combinational_sink_ports="Q" clock="clk"/>
      <port name="E" combinational_sink_ports="Q" clock="clk"/>
      <port name="clk" is_clock="1"/>
    </input_ports>
    <output_ports>
      <port name="Q" clock="clk"/>
    </output_ports>
  </model>
</models>

The ports are not connected combinationally, so combinational_sink_ports shouldn't be there. Expected model:

<models xmlns:xi="http://www.w3.org/2001/XInclude">
  <model name="FF">
    <input_ports>
      <port name="D" clock="clk"/>
      <port name="E" clock="clk"/>
      <port name="clk" is_clock="1"/>
    </input_ports>
    <output_ports>
      <port name="Q" clock="clk"/>
    </output_ports>
  </model>
</models>

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