I noticed that we emit these features only when a particular output of a BUFHCE is in use. But we do not emit them for CLK_HROW tiles in which no BUFHCE is used and there is an active clock wire passing through them.

Consider a design for xc7a50t where the CLK_HROW_TOP_R_X60Y130 tile has active BUFHCEs in it. But the clock signal is routed from a BUFG in CLK_BUFG_BOT_R_X60Y48 tile through CLK_HROW_TOP_R_X60Y78. The "bottom" CLK_HROW tile does not have anything active inside.

In such a design Vivado emits a CLK_HROW_R_CK_GCLKx_ACTIVE feature for the CLK_HROW_TOP_R_X60Y78 tile while SymbiFlow don't. Anyways, the design works correctly in hardware.