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Inference of 3-state IOBUFs in Yosys #1161

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mkurc-ant opened this issue Nov 20, 2019 · 2 comments · Fixed by #1170 or #1195
Closed

Inference of 3-state IOBUFs in Yosys #1161

mkurc-ant opened this issue Nov 20, 2019 · 2 comments · Fixed by #1170 or #1195

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@mkurc-ant
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The current support for IOBUFs (#1148) requires them to be explicitly instantiated and connected directly to a top-level IO port.

Using a top-level inout port directly in the following way won't work:

inout A;

...

wire A_i;
wire A_t;
wire A_o;

assign A_i = A;
assign A = (A_t == 1'b1) ? A_o : 1'bz;

I tried to play with the iopadmap Yosys command but failed to find a working solution. In some cases I ended up with an OBUFT-like cell for the 3-state output and the input taken directly from the pin (not through any buffer). In other cases I had a properly connected IOBUF cell but after optimization its output got disconnected (a bug?).

@mkurc-ant
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The generated verilog for the LiteX design contains such assign statements:

assign eth_mdio = main_ethphy_data_oe ? main_ethphy_data_w : 1'bz;
assign main_ethphy_data_r = eth_mdio;

@mkurc-ant
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YosysHQ/yosys#1530

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