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base repository: GlasgowEmbedded/glasgow
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head repository: GlasgowEmbedded/glasgow
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compare: dbf4de840a77
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  • 1 commit
  • 1 file changed
  • 1 contributor

Commits on Oct 16, 2019

  1. platform.ice40: do not emit debug Verilog. 

    This upstream change broke run-prebuilt and also made every bitstream
ID request slower. It makes sense for a more traditional workflow,
but not so much for Glasgow.
    @whitequark
    whitequark committed Oct 16, 2019
    Copy the full SHA
    dbf4de8 View commit details
Showing with 7 additions and 0 deletions.
  1. +7 −0 software/glasgow/platform/ice40.py
7 changes: 7 additions & 0 deletions software/glasgow/platform/ice40.py
View file
Original file line number Diff line number Diff line change
@@ -10,6 +10,13 @@


class GlasgowPlatformICE40(LatticeICE40Platform):
@property
def file_templates(self):
# Do not require yosys to be present for toolchain_prepare() to finish.
file_templates = super().file_templates
del file_templates["{{name}}.debug.v"]
return file_templates

def toolchain_program(self, products, name):
bitstream = products.get("{}.bin".format(name))
async def do_program():