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base repository: GlasgowEmbedded/glasgow
base: b015750ff242
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head repository: GlasgowEmbedded/glasgow
compare: dbf4de840a77
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  • 1 commit
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  • 1 contributor

Commits on Oct 16, 2019

  1. platform.ice40: do not emit debug Verilog. 

    This upstream change broke run-prebuilt and also made every bitstream
ID request slower. It makes sense for a more traditional workflow,
but not so much for Glasgow.
    @whitequark
    whitequark committed Oct 16, 2019
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