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base repository: m-labs/nmigen
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  • 2 commits
  • 2 files changed
  • 1 contributor

Commits on Sep 21, 2019

  1. hdl.ast: update docs. NFC.

    whitequark committed Sep 21, 2019
    Copy the full SHA
    a13a21c View commit details
  2. lib.fifo: update docs. NFC.

    whitequark committed Sep 21, 2019
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    2dc6ae4 View commit details
Showing with 10 additions and 10 deletions.
  1. +8 −8 nmigen/hdl/ast.py
  2. +2 −2 nmigen/lib/fifo.py
16 changes: 8 additions & 8 deletions nmigen/hdl/ast.py
Original file line number Diff line number Diff line change
@@ -963,29 +963,29 @@ class Array(MutableSequence):
gpios = Array(Signal() for _ in range(10))
with m.If(bus.we):
m.d.sync += gpios[bus.adr].eq(bus.dat_w)
m.d.sync += gpios[bus.addr].eq(bus.w_data)
with m.Else():
m.d.sync += bus.dat_r.eq(gpios[bus.adr])
m.d.sync += bus.r_data.eq(gpios[bus.addr])
Multidimensional array::
mult = Array(Array(x * y for y in range(10)) for x in range(10))
a = Signal(max=10)
b = Signal(max=10)
a = Signal.range(10)
b = Signal.range(10)
r = Signal(8)
m.d.comb += r.eq(mult[a][b])
Array of records::
layout = [
("re", 1),
("dat_r", 16),
("r_data", 16),
("r_en", 1),
]
buses = Array(Record(layout) for busno in range(4))
master = Record(layout)
m.d.comb += [
buses[sel].re.eq(master.re),
master.dat_r.eq(buses[sel].dat_r),
buses[sel].r_en.eq(master.r_en),
master.r_data.eq(buses[sel].r_data),
]
"""
def __init__(self, iterable=()):
4 changes: 2 additions & 2 deletions nmigen/lib/fifo.py
Original file line number Diff line number Diff line change
@@ -240,7 +240,7 @@ class SyncFIFOBuffered(Elaboratable, FIFOInterface):
does not use asynchronous memory reads, which are incompatible with FPGA block RAMs.
In exchange, the latency betw_enen an entry being written to an empty queue and that entry
becoming available on the output is increased to one cycle.
becoming available on the output is increased by one cycle compared to :class:`SyncFIFO`.
""".strip(),
parameters="""
fwft : bool
@@ -404,7 +404,7 @@ class AsyncFIFOBuffered(Elaboratable, FIFOInterface):
on the output, improving timing in case of block RAM that has large clock-to-output delay.
In exchange, the latency between an entry being written to an empty queue and that entry
becoming available on the output is increased to one cycle.
becoming available on the output is increased by one cycle compared to :class:`AsyncFIFO`.
""".strip(),
parameters="""
r_domain : str