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Implement a sanitizer for memory port combinations #12
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Lattice iCE40DRAMNo distributed RAM. BRAMConfigurable as 2048x2, 1024x4, 512x8 or 256x16. Block RAM rules:
Yosys behavior
iCECube behavior
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Xilinx (7 Series and UltraScale)DRAM
BRAMConfigurable as 32768x1, 16384x2, 8192x4, 4096x9, 2048x18, 1024x36, 512x72 (32 Kb) or 16384x1, 8192x2, 4096x4, 2048x9, 1024x18, 512x36 (18 Kb) in SDP mode.
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Lattice ECP5Distributed RAMUses 3 SLICEs, two for memory and one to feed in the write port, to implement a 16x4 RAM. One synchronous write port with enable and one asynchronous read port. The SLICE flip flops can be used to make the read port synchronous. Written data propogates in about 800ps from write clock edge to async Block RAMConfigurable as 16384x1, 8192x2, 4096x4, 2048x9 or 1024x18 true dual port (DP16KD) or 512x36 pseudo dual port (this mode not implemented in Yosys/nextpnr yet, it uses a different PDPW16KD primitive). Rules:
Yosys Behaviour
Diamond BehaviourTBC |
@nakengelhardt Can you explain why does UG473 specify the BRAM dimensions for SDP mode specifically? Is it different for TDP mode? |
Do you mean this?
The aspect ratios supported are different for SDP and TDP mode, yes. Tables 1-11 to 1-14 on pages 29-30 have the valid combinations. |
There are a lot of possible combinations of memory ports and many of them are not legal. This depends on the vendor. In this issue we collect such behaviors to eventually implement a sanitizer, either as a part of nMigen or as a Yosys pass.
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