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AsyncFIFO specifies a transparent read port and that doesn't work on iCE40 across clock domains because it can only insert soft transparency logic. (How did this work on oMigen in the first place?)
This needs to be investigated closely.
The text was updated successfully, but these errors were encountered:
I think this might be because the read port is transparent (as is the default for Memory.read_port(); we should probably make that explicit). But it doesn't make a lot of sense to have a transparent read port on a memory where both ports are in different domains.
How did this work before? Did oMigen emit the wrong kind of read port, and Xilinx quietly ignore it?
AsyncFIFO specifies a transparent read port and that doesn't work on iCE40 across clock domains because it can only insert soft transparency logic. (How did this work on oMigen in the first place?)
This needs to be investigated closely.
The text was updated successfully, but these errors were encountered: