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base repository: m-labs/nmigen
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head repository: m-labs/nmigen
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compare: a1bc2bbeb044
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- 3 commits
- 4 files changed
- 1 contributor
Commits on Sep 20, 2019
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hdl.mem: use 1 as reset value for ReadPort.en.
This is necessary for consistency, since for transparent read ports, we currently do not support .en at all (it is fixed at 1) due to YosysHQ/yosys#760. Before this commit, changing port transparency would require adding or removing an assignment to .en, which is confusing and error-prone. Also, most read ports are always enabled, so this behavior is also convenient.
whitequark committedSep 20, 2019 Configuration menu - View commit details
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lib.fifo: work around Yosys issue with handling of \TRANSPARENT.
Because of YosysHQ/yosys#1390, using a transparent port in AsyncFIFO, instead of being a no-op (as the semantics of \TRANSPARENT would require it to be in this case), results in a failure to infer BRAM. This can be easily avoided by using a non-transparent port instead, which produces the desirable result with Yosys. It does not affect the semantics on Xilinx platforms, since the interaction between the two ports in case of address collision is undefined in either transparent (WRITE_FIRST) or non-transparent (READ_FIRST) case, and the data out of the write port is not used at all. Fixes #172.
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