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base repository: m-labs/nmigen
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  • 3 commits
  • 4 files changed
  • 1 contributor

Commits on Sep 20, 2019

  1. hdl.mem: use 1 as reset value for ReadPort.en.

    This is necessary for consistency, since for transparent read ports,
    we currently do not support .en at all (it is fixed at 1) due to
    YosysHQ/yosys#760. Before this commit, changing port transparency
    would require adding or removing an assignment to .en, which is
    confusing and error-prone.
    
    Also, most read ports are always enabled, so this behavior is also
    convenient.
    whitequark committed Sep 20, 2019
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    4b3a068 View commit details
  2. lib.fifo: work around Yosys issue with handling of \TRANSPARENT.

    Because of YosysHQ/yosys#1390, using a transparent port in AsyncFIFO,
    instead of being a no-op (as the semantics of \TRANSPARENT would
    require it to be in this case), results in a failure to infer BRAM.
    
    This can be easily avoided by using a non-transparent port instead,
    which produces the desirable result with Yosys. It does not affect
    the semantics on Xilinx platforms, since the interaction between
    the two ports in case of address collision is undefined in either
    transparent (WRITE_FIRST) or non-transparent (READ_FIRST) case, and
    the data out of the write port is not used at all.
    
    Fixes #172.
    whitequark committed Sep 20, 2019
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    f9b9c17 View commit details
  3. lib.fifo: fix doc typo. NFC.

    whitequark committed Sep 20, 2019
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    a1bc2bb View commit details
Showing with 7 additions and 5 deletions.
  1. +1 −1 nmigen/hdl/mem.py
  2. +4 −2 nmigen/lib/fifo.py
  3. +1 −0 nmigen/test/test_hdl_mem.py
  4. +1 −2 nmigen/test/test_sim.py
2 changes: 1 addition & 1 deletion nmigen/hdl/mem.py
Original file line number Diff line number Diff line change
@@ -88,7 +88,7 @@ def __init__(self, memory, domain, *, transparent):
self.data = Signal(memory.width,
name="{}_r_data".format(memory.name), src_loc_at=2)
if self.domain != "comb" and not transparent:
self.en = Signal(name="{}_r_en".format(memory.name), src_loc_at=2)
self.en = Signal(name="{}_r_en".format(memory.name), src_loc_at=2, reset=1)
else:
self.en = Const(1)

6 changes: 4 additions & 2 deletions nmigen/lib/fifo.py
Original file line number Diff line number Diff line change
@@ -368,7 +368,8 @@ def elaborate(self, platform):

storage = Memory(self.width, self.depth)
w_port = m.submodules.w_port = storage.write_port(domain=self._w_domain)
r_port = m.submodules.r_port = storage.read_port (domain=self._r_domain)
r_port = m.submodules.r_port = storage.read_port (domain=self._r_domain,
transparent=False)
m.d.comb += [
w_port.addr.eq(produce_w_bin[:-1]),
w_port.data.eq(self.w_data),
@@ -377,6 +378,7 @@ def elaborate(self, platform):
m.d.comb += [
r_port.addr.eq((consume_r_bin + do_read)[:-1]),
self.r_data.eq(r_port.data),
r_port.en.eq(1),
]

if platform == "formal":
@@ -398,7 +400,7 @@ class AsyncFIFOBuffered(Elaboratable, FIFOInterface):
This queue's interface is identical to :class:`AsyncFIFO`, but it has an additional register
on the output, improving timing in case of block RAM that has large clock-to-output delay.
In exchange, the latency betw_enen an entry being written to an empty queue and that entry
In exchange, the latency between an entry being written to an empty queue and that entry
becoming available on the output is increased to one cycle.
""".strip(),
parameters="""
1 change: 1 addition & 0 deletions nmigen/test/test_hdl_mem.py
Original file line number Diff line number Diff line change
@@ -60,6 +60,7 @@ def test_read_port_non_transparent(self):
self.assertEqual(rdport.transparent, False)
self.assertEqual(len(rdport.en), 1)
self.assertIsInstance(rdport.en, Signal)
self.assertEqual(rdport.en.reset, 1)

def test_read_port_asynchronous(self):
mem = Memory(width=8, depth=4)
3 changes: 1 addition & 2 deletions nmigen/test/test_sim.py
Original file line number Diff line number Diff line change
@@ -548,9 +548,8 @@ def test_memory_read_before_write(self):
def process():
yield self.wrport.data.eq(0x33)
yield self.wrport.en.eq(1)
yield self.rdport.en.eq(1)
yield
self.assertEqual((yield self.rdport.data), 0x00)
self.assertEqual((yield self.rdport.data), 0xaa)
yield
self.assertEqual((yield self.rdport.data), 0xaa)
yield Delay(1e-6) # let comb propagate