from nmigen import *
from nmigen_boards.icebreaker import *
from nmigen.lib.cdc import ResetSynchronizer

class UpCounter(Elaboratable):
    def __init__(self, width, init=0):
        self.value = Signal(width, reset=init)
        self.init = init
        self.reset = Signal()
        self.enable = Signal(reset=1)
        self.at_max = Signal()
        self._max = 2**width-1
        self.at_min = Signal()

    def elaborate(self, platform):
        m = Module()
        with m.If(self.reset):
            m.d.sync += self.value.eq(self.init)
        with m.Elif(self.enable):
            m.d.sync += self.value.eq(self.value+1)
        m.d.comb += [
            self.at_max.eq(self.value == self._max),
            self.at_min.eq(self.value == 0),
        ]
        return m


class PLLTest(Elaboratable):
    def __init__(self):
        pass

    def elaborate(self, platform):
        platform.add_resources(platform.break_off_pmod)

        m = Module()

        should_reset = Signal()

        clk_pin = platform.request(platform.default_clk)
        clk_a = ClockDomain('clk_a')
        clk_b = ClockDomain('clk_b')
        m.domains += [clk_a, clk_b]
        m.d.comb += [
            ClockSignal('clk_a').eq(clk_pin),
            ClockSignal('clk_b').eq(clk_pin),
        ]

        m.submodules += ResetSynchronizer(should_reset, domain="clk_a")
        m.submodules += ResetSynchronizer(should_reset, domain="clk_b")

        led_48_counter = DomainRenamer("clk_a")(UpCounter(24))
        led_12_counter = DomainRenamer("clk_b")(UpCounter(24))
        led_hf = platform.request("led_g", 1)
        led_lf = platform.request("led_g", 2)
        m.d.comb += led_hf.eq(led_48_counter.value[-1])
        m.d.comb += led_lf.eq(led_12_counter.value[-1])

        m.submodules.led_48_counter = led_48_counter
        m.submodules.led_12_counter = led_12_counter

        return m

if __name__ == "__main__":
    design = PLLTest()
    ICEBreakerPlatform().build(design, do_program=True)