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e.g. processing:
`include "./outpad.sim.v" `include "./outbuf_vpr.sim.v" (* MODES="NO_OBUF; OBUF" *) module IOB33 (O, T); parameter MODE = "NO_OBUF"; input wire O; input wire T; (* pack = "pack_buf2out" *) wire buf2out; wire no_obuf_O; assign no_obuf_O = O; generate if(MODE == "NO_OBUF") begin OUTPAD outpad(.outpad(no_obuf_O)); end if(MODE == "OBUF") begin OUTBUF_VPR outbuf_vpr(.in(O), .tri(T), .out(buf2out)); OUTPAD outpad(.outpad(buf2out)); end endgenerate endmodule
fails with: KeyError: 'Net id 2 not found'
KeyError: 'Net id 2 not found'
The problem is caused by:
wire no_obuf_O; assign no_obuf_O = O;
The no_obuf_O wire is optimized out so we cannot find it while processing the Verilog
no_obuf_O
The text was updated successfully, but these errors were encountered:
correction: the net is not optimized out. In fact the ID has two names associated with it. This confuses the scripts.
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e.g. processing:
fails with:
KeyError: 'Net id 2 not found'
The problem is caused by:
The
no_obuf_O
wire is optimized out so we cannot find it while processing the VerilogThe text was updated successfully, but these errors were encountered: