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Test and implement CARRY4/XORCY/MUXCY support #262

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litghost opened this issue Mar 29, 2021 · 1 comment
Open

Test and implement CARRY4/XORCY/MUXCY support #262

litghost opened this issue Mar 29, 2021 · 1 comment
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enhancement New feature or request good first issue Good for newcomers

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@litghost
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litghost commented Mar 29, 2021

Current status

The current FPGA interchange implementation never sets placement relative constraints. This will mean that carry chain structures will have a hard timing statifying the DedicatedInterconnect and waste a lot of time in placement strict legalization. nextpnr's relatively constraint system should be usable for this case, with at least 1 exception.

Potential solutions

During packing, chains of cells that have dedicated interconnect need to be detected and those chain structures identified. In the simple case, once the chain is found settings the cell placement constraint will be enough, see https://github.com/YosysHQ/nextpnr/blob/692d7dc26ddf21e2d38dd16aecef652ab4c0d5e3/common/nextpnr_types.h#L168-L175

There is an exception case that is not solvable with the current system from nextpnr, and that has to do with 7-series carry chain that extend across CMTs. It is worth noting that the symbiflow-arch-defs implementation has the same deficiency, so ignoring this case is potentially fine. The specific case in question is what happens if a carry chain extends across the BRKH_CLB tile type that appears between CMTs. In this case the constr_y will be 2 instead of 1. To solve this would likely require either a placement constraint system change or an Arch API change.

@issuelabeler issuelabeler bot added the question Further information is requested label Mar 29, 2021
@litghost litghost added enhancement New feature or request and removed question Further information is requested labels Mar 29, 2021
@litghost litghost added this to To Do in FPGA interchange bootstrapping via automation Mar 29, 2021
@issuelabeler issuelabeler bot added the question Further information is requested label Mar 30, 2021
@litghost litghost added good first issue Good for newcomers and removed question Further information is requested labels Mar 30, 2021
@kowalewskijan kowalewskijan self-assigned this Apr 9, 2021
@kowalewskijan kowalewskijan moved this from To Do to In progress in FPGA interchange bootstrapping Apr 9, 2021
@Subhraneel77
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Hi @litghost I am Subhraneel, I like to Contribute in this project, can you kindly help me up a little bit, how to begin with . I am completely new to open source programming.So, it will be beneficial for me if You kindly help me up.

@kowalewskijan kowalewskijan removed their assignment Dec 19, 2021
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Labels
enhancement New feature or request good first issue Good for newcomers
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