Current Status

In 7-series and UltraScale+, some cells have placement rules that the current FPGA interchange does not express. Following these rules are important for good clock placement. In some cases, it will be required to create valid design. The current FPGA interchange implementation doesnt' detect or implement proper placement in these cases.

Examples

• 7-series CCIO IO pins have a dedicated path from the IO pin to the BUFG/BUFGCTRL if the BUFG is placed in the same half of the fabric.
• 7-series PLL/MMCM's have dedicate paths from other PLL/MMCM's in the CMT's above and below their location
• 7-series PLL/MMCM's have dedicate paths from clock buffers in the same CMT (BUFR/BUFH) or neighboring CMT (BUFMR) or fabric half (e.g. BUFG)
• 7-series IDELAYCTRL have implicit connections to IDELAY2 elements within the same IO bank

These types of constraints are enforced in the symbiflow-arch-def's script https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc/common/utils/prjxray_create_place_constraints.py

Discussion

Some of these rules could be discovered by examine the routing fabric, but it may be easier to constraint these explicitly. In the case of the IDELAYCTRL, these rules have to be supplied, because the routing fabric lacks the connection altogether.