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Option to disable debug verilog generation #623

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rroohhh opened this issue Jul 16, 2021 · 1 comment
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Option to disable debug verilog generation #623

rroohhh opened this issue Jul 16, 2021 · 1 comment
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@rroohhh
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rroohhh commented Jul 16, 2021

The generation of the debug.v can take quite some time (O(10 seconds) for some designs), so especially for flows where only a rtlil file is needed it would be nice to have a option to disable the its generation.
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Having seen just how much time it wastes, I agree that this would be a valuable addition.

@Lunaphied Lunaphied mentioned this issue Apr 5, 2022
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Lunaphied added a commit to Lunaphied/amaranth that referenced this issue Apr 5, 2022
@Lunaphied
build/plat: implement an override disabling debug Verilog generation.
2edd6e1 
Currently debug Verilog generation can take many 10's of seconds.
A new override can now be passed as `AMARANTH_debug_verilog`=0 on
the environment or by setting the `debug_verilog` keyword argument
to `Platform.build()` or `Platform.prepare_toolchain()` to `False`.

Fixes amaranth-lang#623.
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