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Upstream VTR throws error on buffered switches #548

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acomodi opened this issue Sep 22, 2020 · 0 comments
Open

Upstream VTR throws error on buffered switches #548

acomodi opened this issue Sep 22, 2020 · 0 comments

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@acomodi
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acomodi commented Sep 22, 2020

With master+wip and master getting closer, there is one outstanding fix to be done to have an error-free build of Symbyflow tests with upstream VTR.

The error encountered is due to the following code block:

vtr-verilog-to-routing/vpr/src/route/rr_graph_indexed_data.cpp

Lines 369 to 394 in b22e1fe

calculate_average_switch(inode, avg_switch_R, avg_switch_T, avg_switch_Cinternal, num_switches, buffered);
if (num_switches == 0) {
VTR_LOG_WARN("Track %d had no out-going switches\n", itrack);
continue;
}
VTR_ASSERT(num_switches > 0);
switch_R_total[cost_index] += avg_switch_R;
switch_T_total[cost_index] += avg_switch_T;
switch_Cinternal_total[cost_index] += avg_switch_Cinternal;
if (buffered == UNDEFINED) {
/* this segment does not have any outgoing edges to other general routing wires */
continue;
}
/* need to make sure all wire switches of a given wire segment type have the same 'buffered' value */
if (switches_buffered[cost_index] == UNDEFINED) {
switches_buffered[cost_index] = buffered;
} else {
if (switches_buffered[cost_index] != buffered) {
VPR_FATAL_ERROR(VPR_ERROR_ARCH,
"Expecting all wire-to-wire switches of wire segments with cost index (%d) to have same 'buffered' value (%d), but found segment switch with different 'buffered' value (%d)\n", cost_index, switches_buffered[cost_index], buffered);
}
}
}

In particular, VTR throws a fatal error as switches belonging to the same wire segment have different buffered values. This does not happen in the current master+wip, and the code block resposible looks like the following:

vtr-verilog-to-routing/vpr/src/route/rr_graph_indexed_data.cpp

Lines 376 to 414 in f1a3bcc

for (int iedge = 0; iedge < num_edges; iedge++) {
int to_node_index = device_ctx.rr_nodes[inode].edge_sink_node(iedge);
/* want to get C/R/Tdel/Cinternal of switches that connect this track segment to other track segments */
if (device_ctx.rr_nodes[to_node_index].type() == CHANX || device_ctx.rr_nodes[to_node_index].type() == CHANY) {
int switch_index = device_ctx.rr_nodes[inode].edge_switch(iedge);
avg_switch_R += device_ctx.rr_switch_inf[switch_index].R;
avg_switch_T += device_ctx.rr_switch_inf[switch_index].Tdel;
avg_switch_Cinternal += device_ctx.rr_switch_inf[switch_index].Cinternal;
avg_switch_penalty_cost += device_ctx.rr_switch_inf[switch_index].penalty_cost;
num_switches++;
}
}
if (num_switches == 0) {
VTR_LOG_WARN("Track %d had no out-going switches\n", itrack);
continue;
}
VTR_ASSERT(num_switches > 0);
switch_R_total[cost_index] += avg_switch_R;
switch_T_total[cost_index] += avg_switch_T;
switch_Cinternal_total[cost_index] += avg_switch_Cinternal;
switch_penalty_cost_total[cost_index] += avg_switch_penalty_cost;
if (buffered == UNDEFINED) {
/* this segment does not have any outgoing edges to other general routing wires */
continue;
}
/* need to make sure all wire switches of a given wire segment type have the same 'buffered' value */
if (switches_buffered[cost_index] == UNDEFINED) {
switches_buffered[cost_index] = buffered;
} else {
if (switches_buffered[cost_index] != buffered) {
VPR_FATAL_ERROR(VPR_ERROR_ARCH,
"Expecting all wire-to-wire switches of wire segments with cost index (%d) to have same 'buffered' value (%d), but found segment switch with different 'buffered' value (%d)\n", cost_index, switches_buffered[cost_index], buffered);
}
}
}

@acomodi acomodi changed the title VTR throws error on buffered switches Upstream VTR throws error on buffered switches Sep 22, 2020
@acomodi acomodi mentioned this issue Sep 28, 2020
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