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Reduce lookahead creation time for partition regions #1685
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@acomodi I'm guessing you have the most experience with this given the extended map work. Is this something you think is feasible? |
@andrewb1999 I believe that using the full device lookahead file could be done. The only problem I would see in there is the fact that, depending on the architecture file, the segment indexes could have an offset w.r.t. the partition region architectures. For instance, if a partition region lacks some of the segments present in the whole chip (e.g. clock tile related wires), the whole-device lookahead would be unusable. Instead, if there is a prior mapping of segment indices between the partition region architecture and the whole-chip architecture, I believe that the lookahead could be re-built based on that mapping and used for the partition region. I do not have much experience on the delay matrix though, but I think that a subset of the delay matrix corresponding to the partition region grid could be extracted and used as well. |
The delay matrix should be generalizable, because it's totally flat. I think the extensions to the map lookahead that @acomodi has in mind might work. It would be super interesting to see if a A100T lookahead worked well on the A50T and the A200T fabrics too. |
Currently the slowest part of defining and testing designs with partition regions is the time it takes to generate the place delay and router lookahead. I am wondering if there is some way to get a good enough approximation of these files by creating them from pre-generated full chip files rather than generating them from scratch for each new partition region.
A flow like this would allow faster creation of different partitioned designs and more design space exploration opportunities.
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