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Some synthetic IOs unroutable in overlay architecture #1650
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@litghost Let me know what other information would be useful |
Can you provide the relevant Vivado wire names for that pair? |
Inside PR (used for overlay arch): INT_L_X22Y46/WW4A3 |
Updated, previously one of the wires was wrong. |
@litghost Here is a route_diag example from an synth inpad trying to reach an LED real IO:
You can see that the synth IO is actually connected to at least a few local rr nodes, but doesn't seem to be able to reach outside of a small local area. I'm wondering if there is some off by one error with importing switches on the east side of the ROI. |
Okay I have figured out the issue. Turns out I need to be more careful about where the node is driven from. I accidentally picked nodes that were going in the wrong direction for the I/O I wanted to use it for. A check for this should be added after importing node names into the database. |
In the new switch_processing test case provided in #1649 some synthetic IOs are able to be routed and others are not. With the provided verilog for the test case the first error I run into is
although, I can run into other errors and even get it to route if I comment out enough not working synth IOs.
Here are the synth_tiles and architecture currently being generated. The test case can be run locally by cloning #1649 and running the switch_processing_arty_overlay_bit test case.
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