Commits on Aug 26, 2020

1. back.verilog: omit Verilog initial trigger only if Yosys adds it. …

   Verilog has an edge case where an `always @*` process, which is used
   to describe a combinatorial function procedurally, may not execute
   at time zero because none of the signals in its implicit sensitivity
   list change, i.e. when the process doesn't read any signals. This
   causes the wires driven by the process to stay undefined.
   
   The workaround to this problem (assuming SystemVerilog `always_comb`
   is not available) is to introduce a dummy signal that changes only
   at time zero and is optimized out during synthesis. nMigen has had
   its own workaround, `$verilog_initial_trigger`, for a while. However,
   `proc_prune`, while increasing readability, pulls references to this
   signal out of the process. Because of this, a similar workaround was
   implemented in Yosys' `write_verilog` itself.
   
   This commit ensures we use our workaround on versions of Yosys
   without the updated `write_verilog`, and Yosys' workaround on later
   versions.
   
   Fixes #418.

   

   whitequark committed Aug 26, 2020
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