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base repository: amaranth-lang/amaranth
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  • 1 commit
  • 1 file changed
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Commits on Aug 26, 2020

  1. back.verilog: omit Verilog initial trigger only if Yosys adds it. 

    Verilog has an edge case where an `always @*` process, which is used
to describe a combinatorial function procedurally, may not execute
at time zero because none of the signals in its implicit sensitivity
list change, i.e. when the process doesn't read any signals. This
causes the wires driven by the process to stay undefined.

The workaround to this problem (assuming SystemVerilog `always_comb`
is not available) is to introduce a dummy signal that changes only
at time zero and is optimized out during synthesis. nMigen has had
its own workaround, `$verilog_initial_trigger`, for a while. However,
`proc_prune`, while increasing readability, pulls references to this
signal out of the process. Because of this, a similar workaround was
implemented in Yosys' `write_verilog` itself.

This commit ensures we use our workaround on versions of Yosys
without the updated `write_verilog`, and Yosys' workaround on later
versions.

Fixes #418.
    @whitequark
    whitequark committed Aug 26, 2020
    Copy the full SHA
    12beda6 View commit details
Showing with 3 additions and 2 deletions.
  1. +3 −2 nmigen/back/verilog.py
5 changes: 3 additions & 2 deletions nmigen/back/verilog.py
View file
Original file line number Diff line number Diff line change
@@ -13,8 +13,9 @@ def _convert_rtlil_text(rtlil_text, *, strip_internal_attrs=False, write_verilog
script = []
script.append("read_ilang <<rtlil\n{}\nrtlil".format(rtlil_text))

if yosys_version >= (0, 9, 231):
# Yosys 0.9 release has buggy proc_prune.
if yosys_version >= (0, 9, 3468):
# Yosys >=0.9+3468 (since commit f3d7e9a1) emits Verilog without a possible sim/synth
# mismatch, making $verilog_initial_trigger unnecessary.
script.append("delete w:$verilog_initial_trigger")
script.append("proc_prune")
script.append("proc_init")