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base repository: amaranth-lang/amaranth
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head repository: amaranth-lang/amaranth
compare: 07a3685da8e7
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  • 1 commit
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  • 1 contributor

Commits on Aug 26, 2020

  1. back.rtlil: do not squash empty modules.

    In commit 9faa1d3, the RTLIL backend was changed to ignore modules
    without ports completely, since Yosys would recognize empty modules
    as black boxes without explicit `write_verilog -noblackbox` and break
    the design. That change had many flaws:
      * It removed instances without ports, which are used in e.g. SoC
        FPGAs to instantiate a dummy CPU.
      * It removed fragments without ports, which can appear in e.g. SoC
        FPGAs in case the fabric is not connected to any I/O ports.
      * Finally, it was just conceptually unjustified.
    
    This commit changes the logic to actually check for empty fragments,
    and instead of removing them, it adds a dummy wire inside. It would
    be possible to use the Yosys-specific (*noblackbox*) attribute.
    However, it would be necessary to strip it for most targets right
    away, and also the wire doubles as documentation.
    
    Fixes #441.
    whitequark committed Aug 26, 2020
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