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base repository: amaranth-lang/amaranth
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compare: 07a3685da8e7
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  • 1 commit
  • 1 file changed
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Commits on Aug 26, 2020

  1. back.rtlil: do not squash empty modules. 

    In commit 9faa1d3, the RTLIL backend was changed to ignore modules
without ports completely, since Yosys would recognize empty modules
as black boxes without explicit `write_verilog -noblackbox` and break
the design. That change had many flaws:
  * It removed instances without ports, which are used in e.g. SoC
    FPGAs to instantiate a dummy CPU.
  * It removed fragments without ports, which can appear in e.g. SoC
    FPGAs in case the fabric is not connected to any I/O ports.
  * Finally, it was just conceptually unjustified.

This commit changes the logic to actually check for empty fragments,
and instead of removing them, it adds a dummy wire inside. It would
be possible to use the Yosys-specific (*noblackbox*) attribute.
However, it would be necessary to strip it for most targets right
away, and also the wire doubles as documentation.

Fixes #441.
    @whitequark
    whitequark committed Aug 26, 2020
    Copy the full SHA
    07a3685 View commit details
Showing with 5 additions and 3 deletions.
  1. +5 −3 nmigen/back/rtlil.py
8 changes: 5 additions & 3 deletions nmigen/back/rtlil.py
View file
Original file line number Diff line number Diff line change
@@ -831,6 +831,11 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
verilog_trigger = None
verilog_trigger_sync_emitted = False

# If the fragment is completely empty, add a dummy wire to it, or Yosys will interpret
# it as a black box by default (when read as Verilog).
if not fragment.ports and not fragment.statements and not fragment.subfragments:
module.wire(1, name="$empty_module_filler")

# Register all signals driven in the current fragment. This must be done first, as it
# affects further codegen; e.g. whether \sig$next signals will be generated and used.
for domain, signal in fragment.iter_drivers():
@@ -855,9 +860,6 @@ def _convert_fragment(builder, fragment, name_map, hierarchy):
# name) names.
memories = OrderedDict()
for subfragment, sub_name in fragment.subfragments:
if not subfragment.ports:
continue

if sub_name is None:
sub_name = module.anonymous()