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base repository: amaranth-lang/amaranth
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head repository: amaranth-lang/amaranth
compare: 200af07f9f74
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  • 3 commits
  • 3 files changed
  • 1 contributor

Commits on Aug 26, 2020

  1. sim._pyrtl: optimize uses of reflexive operators. 

    When a literal is used on the left-hand side of a numeric operator,
Python is able to constant-fold some expressions:

    >>> dis.dis(lambda x: 0 + 0 + x)
      1           0 LOAD_CONST               1 (0)
                  2 LOAD_FAST                0 (x)
                  4 BINARY_ADD
                  6 RETURN_VALUE

If a literal is used on the right-hand side such that the left-hand
side is variable, this doesn't happen:

    >>> dis.dis(lambda x: x + 0 + 0)
      1           0 LOAD_FAST                0 (x)
                  2 LOAD_CONST               1 (0)
                  4 BINARY_ADD
                  6 LOAD_CONST               1 (0)
                  8 BINARY_ADD
                 10 RETURN_VALUE

PyRTL generates fairly redundant code due to the pervasive masking,
and because of that, transforming expressions into the former form,
where possible, improves runtime by about 10% on Minerva SRAM SoC.
    @whitequark
    whitequark committed Aug 26, 2020
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  2. vendor.xilinx_7series: unbreak. 

    This commit fixes a series of typos introduced in commit 4e208b0.
    @whitequark
    whitequark committed Aug 26, 2020
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  3. vendor.xilinx_{7series,ultrascale}: set BUFG* SIM_DEVICE as appropriate. 

    Fixes #438 (again).
    @whitequark
    whitequark committed Aug 26, 2020
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