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Add support for parsing enum parameter types #22

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imphil opened this issue Sep 28, 2020 · 0 comments

imphil commented Sep 28, 2020

It looks like the type parser isn't able to parse enum types in parameter declarations.

Failing rST code:

.. verilog:parameter:: parameter ibex_pkg::regfile_e RegFile = RegFileFF

   Register file implementation select:

   * ``ibex_pkg::RegFileFF``: Generic flip-flop-based register file

Build error message:

.../integration.rst:131: WARNING: verilog:parameter: Unexpected token Token('TEXT_EXPR', '::regfile_e RegFile = RegFileFF') at column 19:
        parameter ibex_pkg::regfile_e RegFile = RegFileFF
                          ^

        Expected one of: SYM_BRACKET_L, SYM_COMMA, OP_EQUAL, SYM_PAREN_R, SYM_SEMICOLON

The text was updated successfully, but these errors were encountered:

imphil mentioned this issue

WIP: Use Sphinx Verilog domain lowRISC/ibex#1120

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