Skip to content
Permalink

Comparing changes

Choose two branches to see what’s changed or to start a new pull request. If you need to, you can also or learn more about diff comparisons.

Open a pull request

Create a new pull request by comparing changes across two branches. If you need to, you can also . Learn more about diff comparisons here.
base repository: GlasgowEmbedded/glasgow
Failed to load repositories. Confirm that selected base ref is valid, then try again.
Loading
base: 9b02ce6f283f
Choose a base ref
...
head repository: GlasgowEmbedded/glasgow
Failed to load repositories. Confirm that selected head ref is valid, then try again.
Loading
compare: c96e41edf134
Choose a head ref
  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Aug 28, 2020

  1. revC2: add ESD warning to LVDS connector, add note about it not being… 

    … available on future revs
    @electroniceel
    electroniceel committed Aug 28, 2020

    Verified

    This commit was signed with the committer’s verified signature.
    headius Charles Oliver Nutter
    GPG key ID: 8E26FF248BC7AEAD
    Verified
    Learn about vigilant mode
    Copy the full SHA
    c96e41e View commit details
Showing with 30 additions and 1 deletion.
  1. +14 −0 hardware/boards/glasgow/glasgow-cache.lib
  2. +16 −1 hardware/boards/glasgow/io_banks.sch
14 changes: 14 additions & 0 deletions hardware/boards/glasgow/glasgow-cache.lib
View file
Original file line number Diff line number Diff line change
@@ -974,6 +974,20 @@ P 277 1 1 0 265 -343 261 -341 250 -334 236 -325 218 -313 201 -301 187 -292 177 -
ENDDRAW
ENDDEF
#
# Graphic_SYM_ESD_Large
#
DEF Graphic_SYM_ESD_Large #SYM 0 40 Y Y 1 F N
F0 "#SYM" 0 200 50 H I C CNN
F1 "Graphic_SYM_ESD_Large" 0 -250 50 H I C CNN
F2 "" -5 -30 50 H I C CNN
F3 "" -5 -30 50 H I C CNN
DRAW
P 2 0 0 20 -105 -30 170 -130 N
P 208 0 0 5 19 -202 212 -202 212 -201 210 -199 208 -195 205 -190 197 -176 192 -168 187 -159 163 -119 157 -108 139 -78 134 -69 129 -61 124 -54 121 -47 118 -42 115 -38 114 -35 112 -33 111 -34 109 -35 102 -42 98 -48 97 -53 95 -56 93 -62 90 -67 78 -79 73 -83 67 -88 61 -92 55 -97 48 -102 42 -107 36 -111 32 -114 28 -116 24 -119 14 -127 10 -132 6 -138 2 -145 -3 -153 -9 -168 -15 -180 -21 -186 -24 -188 -25 -189 -33 -189 -36 -188 -40 -184 -42 -178 -44 -171 -45 -162 -45 -136 -43 -128 -41 -121 -37 -115 -33 -110 -15 -92 -12 -88 -8 -78 -7 -76 -6 -72 -5 -69 -5 -68 -8 -65 -10 -62 -14 -60 -17 -57 -20 -55 -22 -53 -24 -53 -26 -54 -29 -56 -33 -58 -38 -61 -42 -63 -46 -66 -52 -70 -63 -81 -70 -89 -68 -94 -67 -96 -67 -99 -66 -102 -66 -113 -67 -118 -68 -121 -68 -122 -69 -124 -67 -128 -65 -131 -65 -132 -60 -142 -57 -152 -56 -163 -56 -171 -57 -174 -58 -176 -59 -179 -62 -184 -66 -187 -70 -189 -74 -189 -77 -188 -79 -186 -81 -182 -84 -177 -87 -170 -91 -161 -95 -151 -99 -139 -99 -138 -101 -132 -104 -126 -108 -116 -109 -115 -112 -106 -114 -97 -114 -89 -112 -80 -109 -71 -107 -67 -103 -61 -99 -54 -93 -47 -87 -39 -83 -35 -77 -25 -74 -21 -73 -20 -68 -11 -63 -4 -57 2 -52 6 -46 8 -44 9 -39 10 -32 12 -23 13 -13 14 -1 15 1 15 11 16 20 17 27 17 33 18 38 19 42 20 46 22 49 23 52 25 60 31 68 39 68 41 67 43 65 46 63 50 59 56 56 63 46 79 41 88 26 113 20 122 16 130 12 136 9 141 6 145 4 148 2 152 1 153 -2 153 -2 152 -5 149 -6 147 -8 144 -10 140 -16 130 -20 124 -24 117 -29 109 -41 89 -48 77 -56 64 -74 34 -84 16 -96 -3 -108 -24 -115 -35 -135 -69 -144 -85 -153 -100 -162 -114 -170 -128 -178 -141 -184 -153 -191 -163 -196 -173 -201 -181 -206 -188 -211 -198 -213 -201 -213 -202 -28 -202 -1 -203 19 -202 f
P 4 0 1 20 -210 -200 210 -200 0 150 -210 -200 N
ENDDRAW
ENDDEF
#
# Logic_LevelTranslator_SN74LVC1T45DRL
#
DEF Logic_LevelTranslator_SN74LVC1T45DRL U 0 20 Y Y 1 F N
17 changes: 16 additions & 1 deletion hardware/boards/glasgow/io_banks.sch
View file
Original file line number Diff line number Diff line change
@@ -1674,7 +1674,7 @@ F 3 "" H 3650 2000 50 0001 C CNN
1 3650 2000
-1 0 0 -1
$EndComp
Text Notes 9350 2950 0 50 ~ 0
Text Notes 9450 6450 0 50 ~ 0
The iCE40 LVDS buffers require external\ntermination, which is expected to be provided\non a specially designed daughterboard.\n\nSuggested mating connector:\nSamtec FLE-122-01-G-DV-A
Text Notes 900 7150 0 50 ~ 0
Balls B6 and B7 correspond to GBIN0/1, whose I/O buffers are shared\nwith one of the PLLs. When the PLL is used, it replaces the input buffer,\nand so the pin input is no longer directly available. Because of this quirk\nof the iCE40 architecture, two common goals are in direct conflict:\n * If an applet is clocked externally, this clock should ideally be provided\n on a GBINx pin. (This is recommended but not strictly necessary as it is\n generally OK for a clock to traverse a small amount of iCE40 fabric.)\n * If an applet is using the PLL co-located with the GBIN0 pin and clocking\n it internally, the GBIN0 pin input buffer is lost, and GBIN1 pin input buffer\n may be lost as well depending on the chosen PLL configuration.\nTo resolve this conflict, the I/O pins mapped to GBIN0/1 are mapped to\na different pin (balls B5 and A6) as well, giving gateware maximum flexibility.
@@ -1842,4 +1842,19 @@ Wire Bus Line
5500 3750 5500 5800
Wire Bus Line
9050 3200 9050 5800
Text Notes 9400 2950 0 50 ~ 0
The LVDS connector J5 is considered a \nsecondary connector and will only be \navailable on revC devices. revD and \nfurther are planned to use different \nconnectors.\n\nPorts A and B are the preferred \nconnectors for addons instead.\n
$Comp
L Graphic:SYM_ESD_Large #SYM?
U 1 1 5F4FA0F7
P 7850 6200
F 0 "#SYM?" H 7850 6400 50 0001 C CNN
F 1 "SYM_ESD_Large" H 7850 5950 50 0001 C CNN
F 2 "" H 7845 6170 50 0001 C CNN
F 3 "~" H 7845 6170 50 0001 C CNN
1 7850 6200
1 0 0 -1
$EndComp
Text Notes 8100 6450 0 50 ~ 0
The LVDS connector J5 just \nhas minimal ESD protection.\nUse appropriate ESD handling\nprocedures. Plug and unplug \nonly in completely unpowered \nstate.\n
$EndSCHEMATC