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base repository: amaranth-lang/amaranth
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  • 7 commits
  • 24 files changed
  • 1 contributor

Commits on Aug 27, 2020

  1. _toolchain.cxx: new toolchain.

    @whitequark
    whitequark committed Aug 27, 2020
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  2. _toolchain.cxx: work around PyPy missing LDCXXSHARED sysconfig variable.

    @whitequark
    whitequark committed Aug 27, 2020
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  3. sim._pycoro: make src_loc() more robust. 

      * Guard for finished coroutines.
  * Guard for coroutines yielding from iterators and not generators.
    @whitequark
    whitequark committed Aug 27, 2020
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  4. sim._pyclock: new type of process. 

    The overhead of coroutine processes is fairly high. A clock driver
implemented through a coroutine process is mostly overhead. This was
partially addressed in commit 2398b79 by microoptimizing yielding.

This commit eliminates the coroutine process overhead completely by
introducing dedicated clock processes. It also simplifies the logic
to a simple toggle.

This change improves runtime by about 12% on Minerva SRAM SoC.
    @whitequark
    whitequark committed Aug 27, 2020
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  5. sim.pysim: in write_vcd(), close files if an exception is raised. 

    This also avoids leaving the waveform writer list in an inconsistent
state after an exception.
    @whitequark
    whitequark committed Aug 27, 2020
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  6. sim: split into base, core, and engines. 

    Before this commit, each simulation engine (which is only pysim at
the moment, but also cxxsim soon) was a subclass of SimulatorCore,
and every simulation engine module would essentially duplicate
the complete structure of a simulator, with code partially shared.

This was a really bad idea: it was inconvenient to use, with
downstream code having to branch between e.g. PySettle and CxxSettle;
it had no well-defined external interface; it had multiple virtually
identical entry points; and it had no separation between simulation
algorithms and glue code.

This commit completely rearranges simulation code.
  1. sim._base defines internal simulation interfaces. The clarity of
     these internal interfaces is important because simulation
     engines mix and match components to provide a consistent API
     regardless of the chosen engine.
  2. sim.core defines the external simulation interface: the commands
     and the simulator facade. The facade provides a single entry
     point and, when possible, validates or lowers user input.
     It also imports built-in simulation engines by their symbolic
     name, avoiding eager imports of pyvcd or ctypes.
  3. sim.xxxsim (currently, only sim.pysim) defines the simulator
     implementation: time and state management, process scheduling,
     and waveform dumping.

The new simulator structure has none of the downsides of the old one.

See #324.
    @whitequark
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  7. [WIP] sim: add cxxsim engine.

    @whitequark
    whitequark committed Aug 27, 2020
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