FYI - We are working on making Yosys (through plugins -> https://github.com/SymbiFlow/yosys-symbiflow-plugins and chipsalliance/yosys-f4pga-plugins#18) propagate SDC timing constraints through clock buffers (and generate derived timing constraints through things like PLLs) and then write out a new SDC file with the complete constraint set (against the generated json / blif names). As nextpnr uses Yosys as a front end, it might make it easier for nextpnr to support this type of thing?

Related to #425.

So actually, when you instantiate a PLL, the toolchain creates a generated clock automatically. create_generated_clock is useful primarily in one case: when you have a clock mux. The SDC files can quickly get extremely unwieldy however, if you start stacking the muxes.

The proposal as stated would require an RFC, but a much more practical solution is to add a platform function that both instantiates a BUFGMUX or whatever and adds the requisite constraints. This is a fairly niche use case though and it's a low priority to add something like that.