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base repository: GlasgowEmbedded/glasgow
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base: d73501db7d03
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head repository: GlasgowEmbedded/glasgow
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compare: 7e170bf14902
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  • 1 commit
  • 2 files changed
  • 1 contributor

Commits on Nov 5, 2020

  1. cli, device.hardware: prepend bitstream ID to prebuilt bitstreams. 

    This makes prebuilt bitstreams functionally identical to just-in-time
built bitstreams; there are no warnings any more for using a prebuilt
bitstream that exactly matches the build plan.

Because prebuilt bitstreams are intended for resource constrained
devices, i.e. they are often not easily rebuilt, loading a prebuilt
bitstream with a mismatched ID only produces a warning. (It can't
really be an error given that nMigen-produced RTLIL files embed
file paths from the host system.)
    @whitequark
    whitequark committed Nov 5, 2020
    Copy the full SHA
    7e170bf View commit details
Showing with 21 additions and 8 deletions.
  1. +8 −7 software/glasgow/cli.py
  2. +13 −1 software/glasgow/device/hardware.py
15 changes: 8 additions & 7 deletions software/glasgow/cli.py
View file
Original file line number Diff line number Diff line change
@@ -520,8 +520,7 @@ async def _main():
if args.prebuilt or args.bitstream:
bitstream_file = args.bitstream or open("{}.bin".format(args.applet), "rb")
with bitstream_file:
logger.warn("downloading prebuilt bitstream from %r", bitstream_file.name)
await device.download_bitstream(bitstream_file.read())
await device.download_prebuilt(plan, bitstream_file)
else:
await device.download_target(plan, rebuild=args.rebuild)

@@ -679,9 +678,10 @@ async def wait_for_sigint():
elif args.bitstream:
logger.info("using bitstream from %s", args.bitstream.name)
with args.bitstream as f:
new_bitstream = f.read()
new_bitstream_id = f.read(16)
new_bitstream = f.read()
glasgow_config.bitstream_size = len(new_bitstream)
glasgow_config.bitstream_id = b"\xff"*16
glasgow_config.bitstream_id = new_bitstream_id
elif args.applet:
logger.info("building bitstream for applet %s", args.applet)
target, applet = _applet(device.revision, args)
@@ -748,13 +748,14 @@ async def wait_for_sigint():
logger.info("building RTLIL for applet %r", args.applet)
with open(args.filename or args.applet + ".il", "wt") as f:
f.write(plan.rtlil)
if args.type in ("zip", "archive"):
logger.info("building archive for applet %r", args.applet)
plan.archive(args.filename or args.applet + ".zip")
if args.type in ("bin", "bitstream"):
logger.info("building bitstream for applet %r", args.applet)
with open(args.filename or args.applet + ".bin", "wb") as f:
f.write(plan.bitstream_id)
f.write(plan.execute())
if args.type in ("zip", "archive"):
logger.info("building archive for applet %r", args.applet)
plan.archive(args.filename or args.applet + ".zip")

if args.action == "test":
logger.info("testing applet %r", args.applet)
14 changes: 13 additions & 1 deletion software/glasgow/device/hardware.py
View file
Original file line number Diff line number Diff line change
@@ -366,13 +366,25 @@ async def download_bitstream(self, bitstream, bitstream_id=b"\xff" * 16):
except usb1.USBErrorPipe:
raise GlasgowDeviceError("FPGA configuration failed")

async def download_target(self, plan, rebuild=False):
async def download_target(self, plan, *, rebuild=False):
if await self.bitstream_id() == plan.bitstream_id and not rebuild:
logger.info("device already has bitstream ID %s", plan.bitstream_id.hex())
else:
logger.info("building bitstream ID %s", plan.bitstream_id.hex())
await self.download_bitstream(plan.execute(), plan.bitstream_id)

async def download_prebuilt(self, plan, bitstream_file):
bitstream_file_id = bitstream_file.read(16)
if bitstream_file_id != plan.bitstream_id:
logger.warn("prebuilt bitstream ID %s does not match design bitstream ID %s",
bitstream_file_id.hex(), plan.bitstream_id.hex())
elif await self.bitstream_id() == plan.bitstream_id:
logger.info("device already has bitstream ID %s", plan.bitstream_id.hex())
else:
logger.info("downloading prebuilt bitstream ID %s from file %r",
plan.bitstream_id.hex(), bitstream_file.name)
await self.download_bitstream(bitstream_file.read(), plan.bitstream_id)

async def _iobuf_enable(self, on):
# control the IO-buffers (FXMA108) on revAB, they are on by default
# no effect on other revisions