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base repository: amaranth-lang/amaranth-boards
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head repository: amaranth-lang/amaranth-boards
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compare: 0e95118062b8
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  • 2 commits
  • 1 file changed
  • 1 contributor

Commits on Oct 9, 2020

  1. genesys2: correctly specify I/O attributes for VADJ banks

    @ktemkin @whitequark
    ktemkin authored and whitequark committed Oct 9, 2020
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    65fc46c View commit details

  2. genesys2: convert ulpi to ULPIResource

    @ktemkin @whitequark
    ktemkin authored and whitequark committed Oct 9, 2020
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    0e95118 View commit details
Showing with 4 additions and 10 deletions.
  1. +4 −10 nmigen_boards/genesys2.py
14 changes: 4 additions & 10 deletions nmigen_boards/genesys2.py
View file
Original file line number Diff line number Diff line change
@@ -24,7 +24,7 @@ def __init__(self, JP6="2V5"):
self._JP6 = JP6

def bank15_16_17_iostandard(self):
return "LVCMOS" + self._JP6
return "LVCMOS" + self._JP6.replace('V', '')

default_rst = "rst"
default_clk = "clk"
@@ -142,15 +142,9 @@ def bank15_16_17_iostandard(self):
attrs=Attrs(IOSTANDARD="LVCMOS33")),
Resource("sd_card_rst", 0,
Pins("AE24", dir="o"), Attrs(IOSTANDARD="LVCMOS33")),
Resource("ulpi", 0,
Subsignal("rst", PinsN("AB14", dir="o")),
Subsignal("clk", Pins("AD18", dir="i")),
Subsignal("d", Pins("AE14 AE15 AC15 AC16 "
"AB15 AA15 AD14 AC14", dir="io")),
Subsignal("dir", Pins("Y16", dir="i")),
Subsignal("stp", Pins("AA17", dir="o")),
Subsignal("nxt", Pins("AA16", dir="i")),
Attrs(IOSTANDARD="LVCMOS18")),
ULPIResource(0, data="AE14 AE15 AC15 AC16 AB15 AA15 AD14 AC14",
rst="AB14", clk="AD18", dir="Y16", stp="AA17", nxt="AA16",
clk_dir="i", rst_invert=True, attrs=Attrs(IOSTANDARD="LVCMOS18")),
Resource("vusb_oc", 0,
PinsN("AF16", dir="i"), Attrs(IOSTANDARD="LVCMOS18")),
Resource("eth_rgmii", 0,