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base repository: amaranth-lang/amaranth
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Commits on Nov 6, 2020

  1. vendor.lattice_{ice40,ecp5}: clean up $verilog_initial_trigger wires. 

    These only matter in simulation and after conversion to Verilog.
During synthesis they cause Yosys to produce warnings:

  Warning: Wire $verilog_initial_trigger has an unprocessed 'init' attribute.
    @whitequark
    whitequark committed Nov 6, 2020
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