So, Verilog doesn't support arrays on ports, only vectors. The best way to get around this limitation in Verilog, in my opinion, is to encode the array into a vector. This works even for Arrays of Records.

I suggest perhaps making a PackedArray class (like in SV), derived from Value, that takes a shape and a size. I believe this would also solve the issue of not being able to place an Array inside of a Record.

I'll work on developing an example of it.