Instance \
        (
            pll_module_name,

            i_inclk0=platform.request("clk50", 1, dir="-"),
            o_c0=clk200,
        ))```

The generated code shows the problem:

```verilog
module pin_clk50_1(clk50_1__io, clk50_1__i);
  (* keep = 1 *)
  output clk50_1__i;
  input clk50_1__io;
  altiobuf_in #(
    .enable_bus_hold("FALSE"),
    .number_of_channels(1'h1),
    .use_differential_mode("FALSE")
  ) clk50_1 (
    .datain(clk50_1__io),
    .dataout(clk50_1__i)
  );
endmodule

module top(pwm_0__io, clk50_1__io);
  wire clk50_1__i;
  input clk50_1__io;
  wire clk200;
pin_clk50_1 pin_clk50_1 (
    .clk50_1__i(clk50_1__i),
    .clk50_1__io(clk50_1__io)
  );
SIV_pll_200M \clk200$1  (
    .c0(clk200),
    .inclk0(clk50_1__i)
  );`

Since quartus automatically places an iobuf, the pin_ module isn't necessary at all here: the pll input should be clk50_1__io. Instantiating a PLL needs a way of directly accessing the underlying pin, without any buffers. This can be done with dir="-" when requesting a new clock, but on platforms with one clock this may not be possible