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assert - no upstream connection #29
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@litghost - Any ideas? |
Nevermind, one minute |
@jgoeders It looks the problem is that you decoded the bit -> fasm using an old prjxray-db. I used the latest prjxray-db and saw the following feature in my fasm that was missing from yours:
That first feature explains the missing route. Something to do in the future is always run bit2fasm with |
Thanks! This is very helpful. I'll add that grep check to my flow. I was using the prjxray-db cloned by fasm2bels -- didn't even cross my mind that it was out of date. Thanks for the debug help!! |
I have the following design (dcp and fasm in zip) that was compiled (Verilog to bistream) using Vivado.
design.zip
I'm running into an assertion during
make_routes
:https://github.com/SymbiFlow/symbiflow-xc-fasm2bels/blob/8961d6a3b8c0dad0e3800180d4fe788fe93744bb/fasm2bels/make_routes.py#L625
There appears to be one BUFG used in this tile. It is fed by a wire that seems to come from this INTER to the left, but also from a long route from an IOB (maybe this is normal to be drawn like this?)
The long wire is driven by an IOB input:
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