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vendor.xilinx_7series: byte swap generated bitstream #523

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merged 1 commit into from Nov 3, 2020

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nfbraun
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@nfbraun nfbraun commented Nov 2, 2020

The Zynq driver in the FPGA Manager framework on Linux expects bitstreams that
are byte swapped with respect to what the Vivado command
write_bitstream -bin_file produces. Thus, use the write_cfgmem command with
appropriate options to generate the bitstream (.bin file).

Fixes #519.

The Zynq driver in the FPGA Manager framework on Linux expects bitstreams that
are byte swapped with respect to what the Vivado command
`write_bitstream -bin_file` produces. Thus, use the `write_cfgmem` command with
appropriate options to generate the bitstream (.bin file).

Fixes amaranth-lang#519.
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codecov bot commented Nov 2, 2020

Codecov Report

Merging #523 into master will not change coverage.
The diff coverage is n/a.

Impacted file tree graph

@@           Coverage Diff           @@
##           master     #523   +/-   ##
=======================================
  Coverage   81.38%   81.38%           
=======================================
  Files          49       49           
  Lines        6414     6414           
  Branches     1282     1282           
=======================================
  Hits         5220     5220           
- Misses       1005     1006    +1     
+ Partials      189      188    -1     
Impacted Files Coverage Δ
nmigen/build/run.py 22.05% <0.00%> (ø)

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Xilinx Zynq: generated bitstreams do not work with (recent?) FPGA Manager
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