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base repository: amaranth-lang/amaranth
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head repository: amaranth-lang/amaranth
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  • 15 commits
  • 25 files changed
  • 7 contributors

Commits on Oct 18, 2020

  1. hdl.ir: Update error message for Instance arguments 

    48d4ee4 added the option to specify attributes using Instance arguments,
but the error message wasn't updated accordingly.
    @Xiretza @whitequark
    Xiretza authored and whitequark committed Oct 18, 2020
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Commits on Oct 19, 2020

  1. setup.py: Exclude "tests" package 

    67b957d moved the tests from nmigen/test/ to tests/, and removed the
exclude= parameter from find_packages() in setup.py. However, even if
the new location is not inside the module tree, it is still found by
find_packages(), resulting in a stray "tests" module on the system.
    @Xiretza @whitequark
    Xiretza authored and whitequark committed Oct 19, 2020
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  2. vendor.quicklogic: fix syntax 

    Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
    @whitequark
    Jan Kowalewski authored and whitequark committed Oct 19, 2020
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Commits on Oct 22, 2020

  1. hdl.dsl: error on Elif immediately nested in an If. 

    I.e. on this code, which is currently not only wrongly accepted but
also results in completely unexpected RTL:

    with m.If(...):
        with m.Elif(...):
            ...

Fixes #500.
    @whitequark
    whitequark committed Oct 22, 2020
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  2. sim._pyrtl: sign extend RHS of assignment. 

    Fixes #502.
    @whitequark
    whitequark committed Oct 22, 2020
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  3. tests: make spec directory name unique per test method.

    @anuejn
    anuejn committed Oct 22, 2020
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Commits on Oct 24, 2020

  1. lib.fifo.AsyncFIFO: fix incorrect latency of r_level. 

    Co-authored-by: Andrew Wygle <awygle@gmail.com>
    @anuejn @awygle
    anuejn and awygle committed Oct 24, 2020
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Commits on Oct 25, 2020

  1. CI: disable codecov project status. 

    Every PR should be covered by tests, and codecov patch statuses are
extremely useful. However, codecov project statuses mostly create
noise because project-wide coverage in nMigen is currently primarily
informational.
    @whitequark
    whitequark committed Oct 25, 2020
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  2. back.{verilog,rtlil}: adjust $verilog_initial_trigger insertion. 

    To track upstream changes.
    @whitequark
    whitequark committed Oct 25, 2020
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Commits on Oct 26, 2020

  1. build.dsl: clean up inversion logic. 

      * Add invert= argument to DiffPairs() constructor, like in Pins().
  * Make PinsN() and DiffPairsN() pass invert= to the corresponding
    construtor instead of mutating.
    @whitequark
    whitequark committed Oct 26, 2020
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Commits on Oct 27, 2020

  1. setup: link to latest docs if VCS information is not available.

    @newhouseb
    newhouseb committed Oct 27, 2020
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Commits on Oct 28, 2020

  1. lib.fifo.AsyncFFSynchronizer: check input and output signal width

    @rroohhh @whitequark
    rroohhh authored and whitequark committed Oct 28, 2020
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Commits on Oct 30, 2020

  1. vendor.quicklogic: fix toolchain nomenclature 

    Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
    @whitequark
    Jan Kowalewski authored and whitequark committed Oct 30, 2020
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  2. vendor.quicklogic: utilize internal SoC clock in EOS-S3 

    Signed-off-by: Jan Kowalewski <jkowalewski@antmicro.com>
    @whitequark
    Jan Kowalewski authored and whitequark committed Oct 30, 2020
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Commits on Nov 1, 2020

  1. [WIP] sim: add cxxsim engine.

    @whitequark
    whitequark committed Nov 1, 2020
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