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Artix 200T missing bits #1750

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acomodi opened this issue Nov 4, 2020 · 7 comments
Open

Artix 200T missing bits #1750

acomodi opened this issue Nov 4, 2020 · 7 comments

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@acomodi
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acomodi commented Nov 4, 2020

While adding designs in fpga-tool-perf for the nexys_video board, the following error showed up.

File "/media/newdrive/prjxray/fpga-tool-perf/env/conda/envs/symbiflow-env/lib/python3.8/site-packages/prjxray/fasm_assembler.py", line 190, in parse_fasm_filename
    raise FasmLookupError('\n'.join(missing_features))
prjxray.fasm_assembler.FasmLookupError: Segment DB CMT_TOP_L_LOWER_B, key CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF3_NS.MMCM_CLK_FREQ_BB_NS3 not found from line 'CMT_TOP_L_LOWER_B_X256Y113.MMCM_CLK_FREQ_BB_REBUF3_NS.MMCM_CLK_FREQ_BB_NS3'
Segment DB CMT_TOP_L_UPPER_T, key CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS.PLL_CLK_FREQ_BB_BUFOUT_NS3 not found from line 'CMT_TOP_L_UPPER_T_X256Y96.PLL_CLK_FREQ_BB3_NS.PLL_CLK_FREQ_BB_BUFOUT_NS3'
Segment DB CMT_TOP_L_LOWER_B, key CMT_TOP_L_LOWER_B.MMCM_CLK_FREQ_BB_REBUF3_NS.MMCM_CLK_FREQ_BB_NS3 not found from line 'CMT_TOP_L_LOWER_B_X256Y61.MMCM_CLK_FREQ_BB_REBUF3_NS.MMCM_CLK_FREQ_BB_NS3'
Segment DB CMT_TOP_L_UPPER_T, key CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS.PLL_CLK_FREQ_BB_BUFOUT_NS3 not found from line 'CMT_TOP_L_UPPER_T_X256Y44.PLL_CLK_FREQ_BB3_NS.PLL_CLK_FREQ_BB_BUFOUT_NS3'
Segment DB GTP_COMMON_MID_RIGHT, key GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN2.HCLK_GTP_CK_MUX2 not found from line 'GTP_COMMON_MID_RIGHT_X167Y23.HCLK_GTP_CK_IN2.HCLK_GTP_CK_MUX2'
Segment DB GTP_COMMON_MID_RIGHT, key GTP_COMMON_MID_RIGHT.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX0 not found from line 'GTP_COMMON_MID_RIGHT_X167Y23.HCLK_GTP_CK_IN0.HCLK_GTP_CK_MUX0'
Makefile:43: recipe for target 'top.bit' failed
make: *** [top.bit] Error 1

The problem, as far as I understood, might be related to the fact that the bottom and top rows of the 200T have a non-common structure, with the GTP_COMMON_MID tile in the middle of the row.

Placing the PLL elsewhere, avoiding the top and bottom rows seems to solve the issue.

A similar issue was filed, and I believe we are hitting the same kind of problem here: #1489
@acomodi
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acomodi commented Nov 4, 2020

The image below is from a dcp obtained with the yosys-vivado toolchain in FPGA-tool-perf. The highlighted nets are the CLKIN and CLKOUTs nets that go to/from the PLL in the X1Y0 cmt.

Screenshot from 2020-11-04 12-03-30

The unknown GTP bits are highlighted in the image below, and we are indeed missing those. Given that the routing step passes correctly in VPR, I think that the RR nodes passing through the GTP tile are correctly connected, but we have some missing bits for those pips.
The issue though is that we would need to move the whole fuzzer generation to use the 200T device, as now, IIRC, we are using the 100T.

Screenshot from 2020-11-04 12-11-17

@mkurc-ant
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MMCM tile REBUF PIPs are disabled in 034b now. Enabling them should solve at least some of the missing bits.

@mithro
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mithro commented Nov 13, 2020

@mkurc-ant - What do we need to do to enable the REBUF PIPs? Why were they disabled?

@mkurc-ant
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@mithro I don't know why they are disabled now. A preliminary test I've done shows that the fuzzer solves them successfully. Haven't checked for potential bit conflicts though.

@mkurc-ant
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This should solve the unknown MMCM PIPs: f4pga/prjxray#1498

@acomodi
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acomodi commented Nov 17, 2020

Perfect. The bits to solve now are related to the pips in the GTP_COMMON_MID tile.
Even though the 50T and 100T have the GTP_COMMON tiles, their location at the border of the device makes them not interfering with the clock wires.

Instead, for the 200T, the GTP_COMMON_MID tiles alter the path of the clock wires which would normally get from/to the PLL to/from the BUFHCE tiles.

I am trying to run the fuzzers for the 200T, and see if we can transition to that part in prjxray. This would give us the possibility to write a fuzzer to get the missing bits for those pips (visible in the above screenshot)

@mkurc-ant mkurc-ant mentioned this issue Nov 17, 2020
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@HackerFoo HackerFoo added this to Blocking in Litex w/Linux on 200T Nov 24, 2020
@mkurc-ant
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I have a finding. So the CMT_TOP_L_UPPER_T PIPs with missing bits are actually bi-directional pseudo PIPs. For example we have an entry in the db for CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS3.PLL_CLK_FREQ_BB3_NS but we do not have one for CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB3_NS.PLL_CLK_FREQ_BB_BUFOUT_NS3.

I'm not entirely sure how we model bi-directional PIPs in VPR.

One solution that comes into my mind is to have two entries per bi-dir PPIP for both directions.

@HackerFoo HackerFoo moved this from Blocking to Workaround in Litex w/Linux on 200T Nov 24, 2020
@acomodi acomodi mentioned this issue Dec 9, 2020
Merged
@kgugala kgugala removed this from Workaround in Litex w/Linux on 200T Sep 3, 2022
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3 participants
@mithro @acomodi @mkurc-ant