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Update the subtitle/motto of the project #59

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umarcor opened this issue Oct 29, 2020 · 11 comments
Closed

Update the subtitle/motto of the project #59

umarcor opened this issue Oct 29, 2020 · 11 comments
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@umarcor
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umarcor commented Oct 29, 2020

The subtitle of https://github.com/SymbiFlow, and maybe other places in the docs, state:

Open source flow for generating bitstreams from Verilog.

However, that might be misleading. On the one hand, litex/migen are used too. On the other hand, VHDL (GHDL) and System Verilog (Surelog, Verible) are within the scope of SymbiFlow. Therefore, I would propose changing it to:

Open source EDA flow for generating bitstreams from Hardware Description Languages.


By the same token, I'd propose rewording the first sentence in https://symbiflow.github.io from:

SymbiFlow is a fully open source toolchain for the development of FPGAs of multiple vendors.

to

SymbiFlow is a fully open source mesh of EDA tools for the development targeting FPGAs of multiple vendors.

@pgielda
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pgielda commented Oct 29, 2020

I would suggest avoiding the word EDA if we can. I think "open source flow" or "open source toolchain" is much more understandable outside of the ASIC/FPGA community and at the same time within as both "flow" and "toolchain" are known words.
I think the word "EDA" scares new people away. Just my personal opinion.
Also while I agree that the scope is slowly becoming wider than just (System)Verilog, some of the tools that you mention (e.g. LiteX) are more used for testing than part of the flow itself, some (like migen) are Verilog generators. And I tihnk the words like "flow" and "toolchain" are broad enough to include those tools.
Verible on the other hand is a SystemVerilog linter/formatter - useful again, but hard to say if its part of the toolchain itself.

In other words "toolchain" and "flow" sounds much better than "mesh of EDA tools" in my personal opinion.

@umarcor
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umarcor commented Oct 29, 2020

I agree that "mesh" might not be the best replacement, and I understand that you might want to avoid EDA. My second point is that SymbiFlow is not a toolchain, but multiple toolchains; an ecosystem that puts several tools together and allows users to build the workflow that better suits their needs. I believe it is important to underline the fact that Symbiflow is the integration and the glue between many independent projects. That's why I would try to avoid using "toolchain", in singular. Other than that, "flow" sounds better than "mesh", yet again it's not a single flow but many.

With regard to the first point, while I agree that migen, Chisel, SpinalHDL, Clash, etc. can be considered just tools that output Verilog, I believe there is no need to constraint the scope. Some/many of them can generate VHDL and/or SystemVerilog too. Moreover, SystemVerilog is supported in Yosys through a frontend, just as VHDL is. Hence, from a technical point of view, the heart of the synthesis flows is not better suited for any of them. That's why I think it's better to talk about HDLs (in plural) in such a prominient place. Currently, none of the info in the site (https://symbiflow.github.io/) is specific about one HDL. In fact https://symbiflow.readthedocs.io/en/latest/toolchain-desc/design-flow.html# shows Verilog, SystemVerilog and VHDL, even though Verific is shown only instead of open source frontends.

Overall, IMHO explaining that HDLs other than Verilog can be used, and that multple toolchains are supported, would help bring the attention of a non-negligible subset of the industry which might not find the current wording appealing.

@mithro
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mithro commented Oct 29, 2020

Maybe ecosystem or distribution is a better name than tool chain?

We could also just put an s on the end of toolchain? :-P

@umarcor
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umarcor commented Oct 29, 2020

I like either ecosystem or toolchains. I think that distribution might be misunderstood as a Linux distro.

@umarcor
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umarcor commented Dec 10, 2021

@mithro @pgielda, can we revisit and close this?
What about "Open source ecosystems for generating bitstreams from Hardware Description Languages" or "Open source ecosystems for generating bitstreams from (System) Verilog and/or VHDL"?

@mithro
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mithro commented Dec 28, 2021

@mgielda - What do you think?

@mgielda
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mgielda commented Dec 30, 2021

I agree no motto is ideal but what I did like about the original was simplicity. Let's try to keep that! I think we can swap "Verilog" to "HDLs".

As for "ecosystems", especially in plural, rings a bit fuzzy to me. Maybe simply "toolchains"?

I would also add the word "FPGA" since somehow it was not there. So in full, my proposal:

Open source toolchains for generating FPGA bitstreams from HDLs.

@umarcor
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umarcor commented Dec 30, 2021

I like that!

@mgielda
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mgielda commented Dec 30, 2021

Great! If @mithro, @pgielda and @kgugala agree then I think it's a reasonable change.

@kgugala
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kgugala commented Dec 30, 2021

SGTM!

@pgielda
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pgielda commented Dec 30, 2021

+1

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