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base repository: YoWASP/yosys
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head repository: YoWASP/yosys
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compare: c617815c4e31
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  • 15 commits
  • 2 files changed
  • 1 contributor

Commits on Oct 8, 2021

  1. Update dependencies.

    whitequark authored and actions-user committed Oct 8, 2021
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Commits on Oct 9, 2021

  1. Update dependencies.

    whitequark authored and actions-user committed Oct 9, 2021
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Commits on Oct 12, 2021

  1. Update dependencies.

    whitequark authored and actions-user committed Oct 12, 2021
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Commits on Oct 16, 2021

  1. Update dependencies.

    whitequark authored and actions-user committed Oct 16, 2021
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Commits on Oct 18, 2021

  1. Update dependencies.

    whitequark authored and actions-user committed Oct 18, 2021
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Commits on Oct 20, 2021

  1. Update dependencies.

    whitequark authored and actions-user committed Oct 20, 2021
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Commits on Oct 21, 2021

  1. Update dependencies.

    whitequark authored and actions-user committed Oct 21, 2021
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Commits on Oct 22, 2021

  1. Update dependencies.

    whitequark authored and actions-user committed Oct 22, 2021
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Commits on Oct 26, 2021

  1. Update dependencies.

    whitequark authored and actions-user committed Oct 26, 2021
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Commits on Oct 27, 2021

  1. Update dependencies.

    whitequark authored and actions-user committed Oct 27, 2021
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Commits on Oct 28, 2021

  1. Update dependencies.

    whitequark authored and actions-user committed Oct 28, 2021
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Commits on Oct 30, 2021

  1. Update dependencies.

    whitequark authored and actions-user committed Oct 30, 2021
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Commits on Nov 1, 2021

  1. Update dependencies.

    whitequark authored and actions-user committed Nov 1, 2021
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Commits on Nov 2, 2021

  1. Update dependencies.

    whitequark authored and actions-user committed Nov 2, 2021
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Commits on Nov 3, 2021

  1. Update dependencies.

    whitequark authored and actions-user committed Nov 3, 2021
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Showing with 2 additions and 2 deletions.
  1. +1 −1 SymbiYosys-src
  2. +1 −1 yosys-src
2 changes: 1 addition & 1 deletion SymbiYosys-src
2 changes: 1 addition & 1 deletion yosys-src
Submodule yosys-src updated 60 files
+14 −0 CHANGELOG
+12 −3 Makefile
+5 −0 README.md
+2 −0 backends/verilog/verilog_backend.cc
+99 −37 frontends/ast/ast.cc
+25 −3 frontends/ast/ast.h
+11 −12 frontends/ast/genrtlil.cc
+213 −13 frontends/ast/simplify.cc
+2 −0 frontends/verific/Makefile.inc
+333 −26 frontends/verific/verific.cc
+1 −0 frontends/verific/verific.h
+1 −0 kernel/constids.inc
+755 −0 kernel/ff.cc
+36 −445 kernel/ff.h
+2 −2 kernel/ffmerge.cc
+4 −4 kernel/mem.cc
+7 −2 kernel/rtlil.cc
+4 −3 kernel/rtlil.h
+1,471 −367 manual/command-reference-manual.tex
+5 −1 passes/hierarchy/hierarchy.cc
+1 −1 passes/memory/memory_dff.cc
+10 −10 passes/opt/opt_dff.cc
+7 −32 passes/proc/proc_dff.cc
+4 −7 passes/sat/async2sync.cc
+18 −19 passes/sat/clk2fflogic.cc
+889 −977 passes/techmap/dfflegalize.cc
+4 −5 passes/techmap/dffunmap.cc
+40 −67 passes/techmap/extract_reduce.cc
+4 −3 passes/techmap/flatten.cc
+2 −2 passes/techmap/simplemap.cc
+3 −1 passes/techmap/techmap.cc
+9 −43 passes/techmap/zinit.cc
+6 −7 techlibs/ecp5/cells_map.v
+7 −6 techlibs/ecp5/synth_ecp5.cc
+62 −22 techlibs/ice40/cells_sim.v
+18 −0 techlibs/intel_alm/common/megafunction_bb.v
+3 −2 tests/arch/xilinx/fsm.ys
+21 −0 tests/memories/trans_addr_enable.v
+12 −0 tests/opt/bug3047.ys
+13 −0 tests/simple/memwr_port_connection.sv
+29 −0 tests/simple/signed_full_slice.v
+32 −0 tests/techmap/dfflegalize_adff.ys
+69 −15 tests/techmap/dfflegalize_adff_init.ys
+2 −2 tests/techmap/dfflegalize_adlatch_init.ys
+92 −0 tests/techmap/dfflegalize_aldff.ys
+148 −0 tests/techmap/dfflegalize_aldff_init.ys
+57 −12 tests/techmap/dfflegalize_dff.ys
+110 −28 tests/techmap/dfflegalize_dff_init.ys
+22 −0 tests/techmap/dfflegalize_dlatch.ys
+4 −4 tests/techmap/dfflegalize_dlatch_const.ys
+38 −0 tests/techmap/dfflegalize_dlatch_init.ys
+4 −4 tests/techmap/dfflegalize_dlatchsr_init.ys
+20 −7 tests/techmap/dfflegalize_inv.ys
+2 −2 tests/techmap/dfflegalize_minsrst.ys
+1 −1 tests/techmap/dfflegalize_sr.ys
+5 −5 tests/techmap/dfflegalize_sr_init.ys
+4 −3 tests/techmap/zinit.ys
+3 −3 tests/tools/vcdcd.pl
+31 −0 tests/verilog/unbased_unsized_tern.sv
+6 −0 tests/verilog/unbased_unsized_tern.ys