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XC95288XL and XC95144XL support #285

Merged
merged 2 commits into from
Oct 29, 2021
Merged

XC95288XL and XC95144XL support #285

merged 2 commits into from
Oct 29, 2021

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brainstorm
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Adding support for this Xilinx CPLD after some guidance in:

https://discord.com/channels/613131135903596547/613461005392936961/900928494450638879

After reading about the glasgow-archive in the contribution guidelines, I'll perhaps add the PDF:

https://www.xilinx.com/support/documentation/data_sheets/ds055.pdf

Although the material is quite well covered already in accessions G00014 and G00015?

@brainstorm brainstorm marked this pull request as ready for review October 25, 2021 10:42
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brainstorm commented Oct 26, 2021

The last bits to determine from this changeset are usercode_low/high, according to our IRC discussions... Here's a snippet I took from the __init__.py documentation:

#!/usr/bin/env python

import sys

def jed_to_word_address_mapping(jed_address):
	block_num = jed_address // 432
	block_bit = jed_address % 432
	word_addr = block_num * 15
	if block_bit < 9 * 32:
	  word_addr += block_bit // 32
	else:
	  word_addr += 9 + (block_bit - 9 * 32) // 24

	return word_addr

def word_address_to_fpgm_fvfy_address_mapping(word_address):
	block_num = word_addr // 15
	block_off = word_addr % 15
	dev_addr  = 32 * block_num + 8 * (block_off // 5) + block_off % 5
	
	return dev_addr

jed_addr = int(sys.argv[1])
word_addr = jed_to_word_address_mapping(jed_addr)
print("Word address mapping: {}".format(word_addr))
print("FPGM/FVFY mapping   : {}".format(word_address_to_fpgm_fvfy_address_mapping(word_addr)))

Which yields the following numbers outlined in the docs, for validation:

% ./jed_translate.py 2592
Word address mapping: 90   <---- usercode_low?
FPGM/FVFY mapping   : 192

% ./jed_translate.py 3024
Word address mapping: 105  <---- usercode_high?
FPGM/FVFY mapping   : 224

I built and examined some example JED files I generated with ISE 14.7 with USERCODE 0000 and 1111, by using the -n USERCODE flag (thanks @anuejn) here's the diff which doesn't seem to follow the same pattern(s)? (showing only the relevant changes below for brevity):

-L0010752 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0010752 00000010 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
*****
-L0011264 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0011264 00000010 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
*****
-L0012480 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0012480 00000010 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
*****
-L0012992 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*
+L0012992 00000010 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000*

Running the script above with those address lines:

% ./jed_translate.py 10752
Word address mapping: 373
FPGM/FVFY mapping   : 787

% ./jed_translate.py 11264
Word address mapping: 391
FPGM/FVFY mapping   : 833

% ./jed_translate.py 12480
Word address mapping: 433
FPGM/FVFY mapping   : 915

% ./jed_translate.py 12992
Word address mapping: 451
FPGM/FVFY mapping   : 961

Most probably I'm missing some crucial bit or I've introduced some error in this analysis, happy to revisit it if something is wrong.

@brainstorm
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@whitequark How did you manage to set USERCODEs 0x30303030 and 0xaaaaaaaa on ISE's hprep6 which seems to only support 4 chars?

I'm trying to reduce the degrees of freedom between your analysis (with the XC9572XL) and mine (with the XC95288XL)... I thought I had reproduced it above, but there might be more variation(s) than expected between CPLD models?

/cc @anuejn @rroohhh

Sorry, something went wrong.

@brainstorm brainstorm requested a review from whitequark October 29, 2021 12:07
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brainstorm commented Oct 29, 2021

As per @rroohhh analysis, usercode_low/high is shared across Xilinx CPLD models, see IRC logs for details: https://libera.irclog.whitequark.org/glasgow/2021-10-29

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@brainstorm brainstorm changed the title XC95288XL support XC95288XL and XC95144XL support Oct 29, 2021
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LGTM, but please squash the commits into two; one that fixes the logging issue, and another that adds support for the new devices. Please do use our conventions for commit messages as well.

@whitequark whitequark merged commit 2439f1c into GlasgowEmbedded:main Oct 29, 2021
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Thank you!

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2 participants