As per the discussion in #57 (comment), there is a special case for the 7-series devices (which might be present in other arches as well), for which the route-thru pseudo PIP used in the BUFG site results in a wrong configuration of the BUFG route-thru bel.

Specifically, the CE and S pins of the BUFGCTRL are not correctly handled, and routed to GND (the inverters are enabled by default and the unconnected pins are routed to VCC by default), hence the I0 input is not enabled, resulting in a non-propagating clock from the routed-thru BUFG.

See the discussion in #57 (comment) for more information.